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CPU Clock Speed based on MOSFET Physics Gate Length, Electic Field...
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Agent:
I’m writing a paper about the stagnation of CPU clock speed increases. In the late 90’s and early 2000’s we were seeing insane clock speed increases. In late 2004 the Pentium 4 570 was launched at 3.8 GHz. From what I have found, the fastest manufacturer rated base clock is 4.7 GHz with the AMD FX-9590. I’m ignoring turbo and only looking at single core performance. I have picked a few CPUs from the end of each decade and started with the intel 8088.

What I am trying to do is compare theoretical clock speeds with actually achieved clock speeds. As I understand it, cutoff frequency is a function of electron mobility, electric field, and channel length. I realize that equation 1 is for the ideal case and in an actual MOSFET, the effect of parasitic capacitance will substantially reduce the cutoff frequency. For reference the channel length of the 8088 is 3 um and it topped out at 10 MHz.


Questions:
1.   Is 400 cm^2/V-s reasonable for electron mobility?
2.   CPUs use both nMOS and pMOS. Hole mobility is much lower than electron mobility so we don’t care about nMOS, pMOS is the limiter. What is a reasonable hole mobility?
3.   What should I be plugging in for Vgs and Vt? (I think Vt should be around 0.3V)
4.   How do I calculate the electric field in a CPU MOSFET?
5.   If a CPU lists Vccmax as 1.55 V that is the highest voltage in the CPU. How can I figure out what gate, drain, and source voltages are?

Basically I want to go from 1980 to 2004 when clock speed actually scaled and come up with a reasonable approximation of calculated vs. actual clock speed based on transistor physics.


If I ignore Vgs and Vt and just plug in thermal voltage, 0.0259, it actually looks pretty reasonable until the gate length shrinks to 130 nm. Any help would be appreciated. Thanks!
T3sl4co1l:
Electron mobility is higher than that, but mind it also depends on doping density, and density has been getting higher and higher as feature scales get smaller (they famously claim transistors have about one atom of dopant in them nowadays, which if you consider the volume of such a transistor, is actually an incredibly high doping rate for silicon, IIRC).

There are special effects for short channels that I don't know about, and there's also the contribution from SOI where (usually) an oxygen layer is implanted beneath the transistor, and annealed to grow a solid oxide (SiO2 glass) layer; the reduction in leakage current and capacitance provides a big kick.  And everything else they've done: copper interconnects, high-K gate oxide, etc. etc.

Some of these aren't new -- the RCA 1802 was SOI (epitaxy on sapphire, wasn't it?), and performed well for its day (its strange architecture notwithstanding!), as well as being rad-hard.

May also be worth including some "honorable mentions", like Cray's GaAs design, which belched out so much heat it had to be cooled with Freon (unless I'm mixing up various things here, which may be :P ).  Sure it was fast (GaAs NMOS has very nice mobility), but it was "Class A" because there was no complement (GaAs hole mobility is pitiful, better to use resistors(!)).

Similarly there were quite fast machines in the 60s and 70s, thanks to ECL -- but they were hard to design and build (CNC wire-wrap machines were a thing, and not just for single wires, but for twisted pair as well -- a hard requirement for ECL signal quality!), and very, very hot.  VLSI CMOS quickly surpassed these through the 70s and 80s.  Since you're concentrating on CMOS, maybe this isn't necessary.

Tim
Agent:
I'm actually examining materials with higher mobility that can support higher electric fields without breakdown. I'm attempting to find some reasonable trend within the achieved Si clock speeds that can be applied to a new material. e.g. Silicon theoretically can reach X GHz, but in actuality it reaches Y GHz. New material theoretically can reach X GHz, using info from Si as a base it could probably reach Y GHz.

When people attempt to break world records for clock speed with liquid nitrogen are they using stock motherboards with no electrical modifications? I assume that MOBO manufacturers didn't have this in mind when they designed them. Which makes me think is it the CPU or motherboard that is limiting liquid nitrogen overclocking? It seems like when people go for records they have multiple CPUs on hand...so the CPU is the limiter?

What is actually happening with liquid nitrogen cooling? The processor is cooled down, therefore the power can be increased without over heating. Which means the voltage is higher, increasing the electric field, making the electrons travel faster, so the transistor can switch faster. Or does it have something to do with interconnects resistance being decreased, improving the RC time constant? Both?
Kilrah:

--- Quote from: Agent on December 11, 2018, 07:41:27 pm ---When people attempt to break world records for clock speed with liquid nitrogen are they using stock motherboards with no electrical modifications? I assume that MOBO manufacturers didn't have this in mind when they designed them.

--- End quote ---
Yup, but there ARE mobos made for overclocking (manufacturers do care about that, gives them visibility plus they can sell related products that don't cost a lot more to make with comfortably inflated margins) and that's what they use. Overclocking contests usually care only about the highest core clock figure so that's the only thing that gets boosted like crazy, chipset/memory/peripherals stay close to their normal clocks. So all that really gets extra stress on the mobo is the power supply section, and that's seriously beefed up on these.
Don't think they go so far as to optimize the PCB traces specifically for higher clocks or binning the chipsets.


--- Quote from: Agent on December 11, 2018, 07:41:27 pm ---What is actually happening with liquid nitrogen cooling? The processor is cooled down, therefore the power can be increased without over heating. Which means the voltage is higher, increasing the electric field, making the electrons travel faster, so the transistor can switch faster. Or does it have something to do with interconnects resistance being decreased, improving the RC time constant? Both?
--- End quote ---
I'd say mostly the former, with a little bit of the latter. They push the voltage up A LOT.
T3sl4co1l:

--- Quote from: Agent on December 11, 2018, 07:41:27 pm ---When people attempt to break world records for clock speed with liquid nitrogen are they using stock motherboards with no electrical modifications? I assume that MOBO manufacturers didn't have this in mind when they designed them. Which makes me think is it the CPU or motherboard that is limiting liquid nitrogen overclocking? It seems like when people go for records they have multiple CPUs on hand...so the CPU is the limiter?

What is actually happening with liquid nitrogen cooling? The processor is cooled down, therefore the power can be increased without over heating. Which means the voltage is higher, increasing the electric field, making the electrons travel faster, so the transistor can switch faster. Or does it have something to do with interconnects resistance being decreased, improving the RC time constant? Both?

--- End quote ---

Yes, it's all about the silicon.

Rds(on) (or more directly, mobility) has a positive tempco.  Vgs(th) also has a negative tempco, so higher voltages are needed, to some extent.  Capacitance stays mostly... well, it has a tempco, but not as strong, AFAIK.

So, cool it, crank up the voltage, crank up the clock, crank up the voltage some more, crank a shitload of amps, dump the nitrogen in, and watch it boil away with 5GHz underneath or whatever.

What happens at the board level is pretty irrelevant.  FR-4 is a shitty material no matter how you cut it; board-level interfaces are already designed to accommodate this.  For example: LVDS and SSTL/GTL signalling to deal with noise; transmitters with preshoot to compensate for HF loss; receivers with hysteresis (schmitt trigger), hold-off (ignores bouncing after the received edge, but well before the next expected edge), voltage reference (differential in some way), automatic skew adjustment, clock recovery, etc.

All sorts of things that may be familiar from facility-level comms (1000BASE-T, say), at lower symbol rates (~100s megs), but these are exactly the kinds of lengths necessary to deal with proportionally shorter distances at proportionally higher symbol rates.  Crazy stuff. :)

I don't know that they're having to go crazy with signalling within a single chip (yet?), but the RC transmission line delay there is even worse, so it has to be buffered just right, at least.

Tim
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