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Crosstalk/Ghosting/offset on ADC input
zer0c00l:
I have an ADC circuit which uses all 8 channels of AD7689. The inputs of the ADC are driven by LT6010 opamp, and have a low pass filter. All 8 channels of the ADC (AD7689) have the same driving circuit. Every other input of the ADC always shows a 3.1mV signal whenever a full scale voltage is applied to the adjacent channel. For example when I apply 5v to channel 1 and short channel 2, channel 2 will read 3.1mV, and all other channels will show 0v. Similar thing happens with channel 3, and 4, and so forth. Now if I remove the capacitor (C152) which is part of the RC filter this problem goes away, and the adjacent ADC input fluctuates between 0.1mV to 0.5mV. An input on channel 1 only effects channel 2.
Another thing I noticed was that if I read these channels with longer delay then I don't see this problem. Like If i wait 800 microseconds after reading channel 1, I won't see 3.1mV on channel 2. Is RC filter designed wrong
jbb:
I haven't used that exact chip, but the AD7689 is a SAR type with an input multiplexer, i.e. one converter shared across several inputs.
What I find suspicious is that the cross-talk happens in channel sequence.
SAR ADCs have sample and hold capacitors, i.e. analog memory. If this capacitance isn't fully charged during the acquisition time, the sample caps will still 'remember' something from the previous channel. Suggest you read the "Analog Inputs" and "Configuration Register" sections of the data sheet and check things are OK. The acquisition time seems to be fixed at 1.8us minimum.
zer0c00l:
--- Quote from: jbb on June 02, 2020, 12:15:59 am ---I haven't used that exact chip, but the AD7689 is a SAR type with an input multiplexer, i.e. one converter shared across several inputs.
What I find suspicious is that the cross-talk happens in channel sequence.
SAR ADCs have sample and hold capacitors, i.e. analog memory. If this capacitance isn't fully charged during the acquisition time, the sample caps will still 'remember' something from the previous channel. Suggest you read the "Analog Inputs" and "Configuration Register" sections of the data sheet and check things are OK. The acquisition time seems to be fixed at 1.8us minimum.
--- End quote ---
Thanks for the response. The configuration register section doesn't really have anything useful for this situation. The only useful thing that I can find from the Analog Inputs section was the bit about settling time
What I understand from that is that the problem might be that the settling time for my RC circuit is higher than what is required from the ADC
MasterT:
Probably, S/H capacitor of the ADC is transferring charge to 0.1 capacitor of the next channel as soon as switching to the next channel happens. Lowering RC time constant would resolve an issue, 2k R is too high value to drain excessive voltage spike in reasonable time frame - 100 nsec or less
zer0c00l:
--- Quote from: MasterT on June 02, 2020, 03:59:42 am ---Probably, S/H capacitor of the ADC is transferring charge to 0.1 capacitor of the next channel as soon as switching to the next channel happens. Lowering RC time constant would resolve an issue, 2k R is too high value to drain excessive voltage spike in reasonable time frame - 100 nsec or less
--- End quote ---
The values for R and C were chosen to give a cutoff frequency of 795Hz, and filter high frequency noise. using a lower R does seem to resolve the problem, but it increases the cutoff frequency, and the adjacent channel seem to pickup fluctuations/noise
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