I verified the 10M is ~10M with my DMM.
I doubt static is the issue as I've used multiple boards with different chips on them (not just new crystal but new everything). I used JLPCB for both assembly/fab. No idea what the odds are they'd ESD all of the chips (low I assume). I can't verify the capacitance of C3/C4 as my DMM isn't good enough (reads zero).
I'm not too worried about C3/C4 since based on my reading they wouldn't be causing these kinds of issues (just a few percent errors at most). I ordered 2.7pF which I'm hearing is too low. Though now I'm confused because I didn't think it varied with voltage.
I must be doing something wrong because I've tried everyone's advice and it only ever seems to work when I unplug it...
Relax. Nothing varies with voltage in this case.
But frankly, your original schematic was not good, and I urge you to redo it, and show it here. You're welcome to copy it from mine in post #15.
Concerning Pierce oscillators: basically a linear inverting amplifier with a 180 degrees feedback element (the crystal).
The amplifier: a CMOS inverter biased to linear operation with a feedback resistor (5...10 Mohm).
The crystal: placed between input and output of the amplifier.
Drive level for the crystal: dependent on the type of crystal, limited by a series resistor when needed.
Load capacitance: the two load capacitors provide this as required in the crystal data sheet. It's the series capacitance of the two load capacitors. So for a crystal needing a load capacitance of 7.5 pF, two 15 pF capacitors are right.
Except they aren't .
Capacitance at the IC needs to be included. For the 4069U (in post #15) it's 5 pF at the input, which will be in parallel to the real load capacitor. The output can be ignored, as the power limiting resistor effectively blocks any influence there.