Board review request (Keyboard prototype)

[Jonathon_Doran]

Thanks again to those who answered my questions on USB and routing.  I think I have something worth showing.  I would very much appreciate any of you taking a moment to comment / offer suggestions for improvement.

This is my first PCB of any complexity in a long time (25 years or so).  So I am still learning, and expect that I have met the bare minimum expectations.  Maybe something worth a C.  But the only way that I'll improve is with some feedback.

The layout is a screen capture from Kicad.  All of the plot and print functions wanted to give me Gerbers.  Maybe everyone here is happy to look at those, but this view is the clearest to me.  Perhaps if I could convince Kicad not to print the fill zones.  (There is a ground fill on both the top and bottom layer).

This is a 2 layer board.  Keyboards can get quite large by necessity, and moving to four layers will triple the cost without bringing me much in return.  One four layer board vs three iterations (minus shipping).  Front copper is in red, bottom copper is in green.  For the matrix, columns are on the front and rows are on the rear.  I have the keyboard diodes on the rear as well -- I am torn about trying to bring them to the front.  I haven't sketched it out, but having them on the columns instead of rows is probably fine (and easier to solder).

The schematic is divided into sections with blue lines.  Someone expressed a dislike for this, and I'll take it into consideration.  As a novice I have always appreciated schematics divided like this.

I could not include the entire switch matrix, but enough is shown in the layout to give the general idea.

The schematic is supplied as a PDF as it is more readable.

Thanks for listening.

[TomS_]

That miniscule VCC trace gives me the heebie-jeebies.

Any reason not to have gnd fill on one side and VCC fill on the other?

[ajb]

A key thing that will help keep a clean layout and maximize your ground pour area is to try to keep all of the tracks on one layer horizontal and all of the tracks on the other layer vertical.  Doesn't matter which layer is which, and you can even swap which layer is which in different parts of the board depending on what makes sense for that area, but in general it makes two layer routing a lot easier.  You can eliminate some vias by switching those lower tracks that come off horizontally from the bottom right side of the MCU to the top layer and that vertical track to the bottom.  See attached.  You can flip the diodes to the top or not, the switches have built-in vias in the form of the PTH pads, so it's easy either way. 

It's not an electrical issue to have traces at all sorts of angles, but it generally makes things easier if you keep tracks to 45/90 degree angles.  Otherwise the way the tracks stack up in a tight routing area gets weird, and it also just looks kinda sloppy (unless you're going for the old-school hand-taped layout look, but that's not what you've got here ). 

In your other thread you said you were using an AT90USB1286, does that call for series resistors on the USB lines?  You probably want to replace the diodes there with an ESD diode array designed for USB, these are usually four or six pins and include both steering diodes and a zener to clamp the power rail, so it's more comprehensive protection and it's designed to have electrical properties compatible with USB signaling.  The series resistors should only be included if called for in the device datasheet usually. 

Another thing to watch out for is the way that your tracks intersect component pads.  When you have small chip components, ideally you want tracks to either come off of the 'end' of the pad, or have two tracks coming off of the 'sides' of the pad, so that the copper attached to the pads is more-or-less symmetrical.  You also want the amount of attached copper to be relatively balance between the two pads of the chip component.  This is all to ensure that when the board is reflowed the solder on both ends of the components flows at about the same time, which helps improve component centering and reduce the chances of the part tombstoning or otherwise pulling out of alignment.  More generally, keeping to this pattern on all pads promotes good fillet formation which slightly improves joint reliability and also makes the joints easier to inspect.  I know I've seen an appnote or article that explains this better with nice diagrams, but this is the best thing I can find at the moment: https://www.pcbcart.com/article/content/design-requirement-of-SMT-PCB-2.html.  This is a bit of a fine detail that you have to worry more about when you get to 0402 and smaller parts, and you can get away with less ideal connections on larger chip components, but it's good to keep in mind and try to accommodate when you can.  This applies especially to the decoupling capacitors. 

With decoupling caps in particular, the preferred routing is generally to place them as close as possible to pairs of power pins, and run a track from each pin 'through' each pad of the cap to a via on the other side.  I've attached a screenshot of a layout that shows this practice, as well as a mostly successful attempt at keeping all of the tracks connected to the pads of chip components in the optimal way.  Also note the trick of routing a few tracks out from the inside of the QFP pads, this can sometimes really simplify some challenging routing problems.  Yellow-hatched tracks are Vcc, blue-hatched tracks are Gnd.

[Jonathon_Doran]

Thanks very much for the responses, I will carefully consider everything.

Tom's heebie-jeebies must be dealt with.  I'm not sure if I want to do a Vcc pour, but there is nothing stopping me if I am prepared to drop vias to ground.  As I believe the return path likes to travel under the original signal (if I understand correctly), then there isn't much of a need for a top ground layer.   At the very least, my Vcc traces will be considerably widened.

Ajb's effort to modify my drawing definitely exceeded my expectations.  I had a preconceived notion of the keyboard matrix rows on one layer and columns on another.  But there is no reason I cannot move the rows to the top.  I need to double check the clearance for the diodes if I'm putting them under the switch,  but they are surface mount parts.  I could also move them off to the side.

I'll make a pass to dress up the trace angles.  I tried a bit the first go around, but obviously did not follow through.

The AT90USB1286 does indeed call for series resistors on the USB differential pair.  And I had a PRTR5VOU2X in the circuit, but took it out because I was having trouble routing it.  The feedback that I received was that I was overthinking ESD protection on USB.  But I think the real reason I axed the part was that I was having trouble sourcing it.  The ultra low capacitance of that part was nice.

Some things I have learned that I never considered before:  The trick of routing traces "through" a decoupling cap.  And the need to have traces come off pads at 90-degree angles to the parts.  I will start doing this from now on!

On the attached screenshot, I see a few traces sneaking under the QFP     It also looks like Vcc got routed on the bottom layer in places, with much larger trace width than on the top.  But the same point-point-point routing I was concerned about.  I'm studying that image a lot.  I see all sorts of "problems" that I was worried about, and how they were solved (like pull-up resistors joining a line at a 90-degree angle -- wouldn't that risk signal reflections?).

I'll post an updated drawing when I have a bit of time, maybe in a week or so.  I'd really like a good shot at getting this board "right" the first time so that I don't go through all the trouble of assembling a doomed board.

[thm_w]

I see all sorts of "problems" that I was worried about, and how they were solved (like pull-up resistors joining a line at a 90-degree angle -- wouldn't that risk signal reflections?).

At these frequencies its not a problem at all.  I'm sure if you run DRC and it passes, electrically the board will work fine.

To me the question is:
- mechanical fitment
- mechanical positioning (eg positioning of the switches are where they can be accessed)
- is there anything you'd want to add later on

eg you might consider adding a few test points to your spare IO, in case you think of another signal you want to add to your board.

[ajb]

I'm not sure if I want to do a Vcc pour, but there is nothing stopping me if I am prepared to drop vias to ground.  As I believe the return path likes to travel under the original signal (if I understand correctly), then there isn't much of a need for a top ground layer.

Well, really return currents will be concentrated in the path that presents the lowest impedance.  At low frequencies, this is based on the DC resistance, and with an uninterrupted ground plane that would be a straight line.  At high frequencies, the inductance of the path becomes more important, and the lowest inductance path is the one that has the smallest enclosed loop area.  With an uninterrupted ground plane that means currents flowing under the trace, because that makes the loop area very small (would be zero if the trace was infinitely close to the ground plane, but with a thin dielectric between them it's still very small). 

Of course in the real world, ground planes are never uninterrupted.  Even with a multilayer board and dedicated plane layers you still have vias punching holes through the plane wherever a track needs to change layers, and if you have a bunch of tracks changing layers in one area you can end up with quite a big hole in the ground plane.  The return currents for any track that passes over that hole will need to detour around it, which increases the loop area (and may increase the DC resistance too, depending).  In a board without dedicated plane layers, where you need to use the layer with your ground pour for routing, you have even more/larger holes created by the tracks on that layer.  Sometimes none of this really matters, there are tons and tons of two-layer boards with little or no appreciable ground pour that work just fine.  But when it does--which it does more and more often as processing and interfaces get faster and faster even in cheap devices--a reasonable solution is to pour ground on top and bottom layers and stich them together with vias.  The top layer spans the gaps in the bottom layer and vice versa, and with vias near enough to all of the places where a track jumps layers the return currents can jump layers as well.  When done well, this is a good enough approximation of a single uninterrupted ground pour for many applications.  The photo I shared earlier has top and bottom ground pours--honestly the top pour wasn't terribly necessary, but it's a 2oz copper board and most of it is big top-side polygons for power handling, so pouring the rest of the top helps keep the copper balanced over the board which reduces warping and promotes more even heating during soldering--but you'll see how the top pour is stitched to the bottom.  Of course on this part of the board the top side is dominated by all of the signals that need to fan out of the MCU and there just isn't a lot of room left for the top pour.  You can pour the top with Vcc and instead of stitching the top and bottom with vias stitch them with decoupling caps which provides much of the same benefit as two ground pours, but IME it's not that often I need Vcc in enough places where that makes sense.  Easier to route Vcc with tracks and just decouple it properly.

Now does any of that matter for your keyboard matrix? No, probably not.  With a newer high performance MCU you might want to make sure your pin drive strength was not set any higher than necessary (because a high drive strength will produce very fast edges when a pin changes state, which is good when you are using it for a high speed interface, but can cause EMI issues if not done carefully), but that's not going to be much of an issue on a 16MHz AVR.  The area around the MCU, including the power distribution to it, is a lot more important, because you have the USB interface to consider but also because the MCU core itself has a constantly changing internal state consuming a pulse of current on every clock edge.  The whole point of putting those decoupling capacitors right next to the chip is to create a very short loop between a local supply of energy (the cap) and the AC load (the MCU) so that inductance is minimized, which keeps the supply voltage seen at the MCU pin stable and prevents that high frequency content from hitting the larger power distribution network on the board where it can cause other problems.  I've crudely sketched in a few different loops on the screenshot I shared earlier.  Arrows indicate conventional current flow direction, and where the lines pass through the IC they are passing through the internal circuitry.  Note that the decoupling caps provide very small loop areas to and thus minimal impedance to supply fast current pulses to the MCU, then there's a larger set of loops to transfer energy from the local bulk cap to the decoupling caps, and still a larger loop that feeds the local bulk cap from the supply.  There are also loops showing the MCU driving external loads. In reality none of these loops are truly independent, and there is never perfect isolation of currents between them, but this makes it easier to visualize.  Note that these are roughly the AC paths, for a steady state load like an LED or something the capacitors are not relevant. 

On the attached screenshot, I see a few traces sneaking under the QFP     It also looks like Vcc got routed on the bottom layer in places, with much larger trace width than on the top.  But the same point-point-point routing I was concerned about. 

 

There's nothing wrong with point-to-point routing of a power line in many cases, provided the overall impedance is low enough for the expected load.  This particular board is about as complex as your keyboard, in terms of the things that matter to this kind of routing.  There's only the one MCU and some LEDs and pullups supplied by Vcc, no other ICs, so the track here is fine.  As above, the loops are small and the DC currents are minimal, so no trouble here.

(like pull-up resistors joining a line at a 90-degree angle -- wouldn't that risk signal reflections?).

Nah, you have to be working with much higher frequencies to worry about that sort of thing.  Lots of Ethernet PHY and switches use pin strapping for configuration, and to reduce the number of pins required they read a pull-up or pull-down resistor connected to IO lines at power up.  It's not uncommon to require resistors on the MII signals, which are clocked at 25/50MHz on 100MBit parts.

[Nominal Animal]

Love the AT90USB1286, was my first microcontroller (Teensy++2.0).  Still use a Teensy++2.0 for occasional tests, so if there is some behaviour you want someone else to test on a different AT90USB1286 board, do feel free to PM or email me.

The datasheet says USB D- (2.2.10) and D+ (2.2.11) need 22 Ohm resistors (in series, between the USB connector and the pin), and UCAP (2.2.14) needs a 1µF bypass capacitor to ground.

The older Atmel version datasheet (which you can find at PJRC) has additional information, so if you reuse older chips, there might be slight differences.  For example, the older datasheet highly recommends 10µF from VBUS to ground at the chip, but the newer does not.  I'm hoping the later device iterations got a better internal voltage regulator or something that made that recommendation obsolete, but personally, I would reserve a 0805-sized pad next to the chip for that since you seem to have the room, just in case.

Me like the per-button diodes but would also prefer thicker traces everywhere for purely mechanical reasons.  Soda spills and such, you see.

I would also consider a 1µF from Vcc to ground, and maybe even a ferrite in the +5V supply line northeast of C6 (with a thicker power trace!).  Are they required? No!

But, it seems that development boards that do have them, feel stabler in my uses.  Perhaps I'm imagining things, or perhaps my cheap USB leads are antennas in disguise, or it is due to something completely different and not just high-frequency noise in my +5V USB lines like I suspect it might be; me being just a software-oriented hobbyist and not an EE at all.  I do regularly use cheapie eBay <$10 USB isolators based on ADuM3160 and cheap isolated DC-DC converters, so perhaps that is core reason in my case; they do have high-frequency switchers and not many components for filtering.  But, since a ferrite bead with less than 50mOhm DC resistance, maximum DC current well over an ampere, and an impedance over 120 Ohms at 100 MHz costs less than ten cents in singles, (and in the same vein, since you already use an 1µF cap for the UCAP pin, adding another for VCC) seems obvious belt-and-suspenders to me: not necessary, but might make the difference between the keyboard being rock solid and sometimes cranky due to noise on the USB 5V line.  You can always omit them at board build time to reduce the cost (although the ferrite bead would need to be replaced with a short).

Edited; forgot to mention: Microchip appnote AN_7602, also known as AVR271: USB Keyboard Demostration, uses the STK525 starter kit to implement an USB keyboard.  The STK525 series 6 uses ATmega1286, so the USBKEY_STK525-series6-hidkbd-2_0_3-doc.zip in the AVR271_USB_Keyboard.zip that you can download off that link, is more or less directly applicable to your project here.  Even if only as a reference into how Atmel/Microchip envisions the MCU to be used for this, it is certainly informative.