Author Topic: Curious question about NMOS vs CMOS - why isn't NMOS capable of static operation  (Read 1840 times)

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Offline alank2Topic starter

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Curious question about NMOS vs CMOS - why isn't NMOS capable of static operation
 

Online coppice

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Nobody really makes NMOS chips any more, but most NMOS logic was static.
 

Offline amyk

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It can be, but even in static state there will be significant power dissipation from the load "resistors".

 

Offline David Hess

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A cursory search shows that NMOS, PMOS, and HMOS static devices were available.  Higher performance logic built on these processes often used dynamic logic for large combinatorial blocks as is the case with CMOS.
 

Offline T3sl4co1l

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They didn't because it was hella inefficient and they took shortcuts wherever they possibly could -- i.e., dynamic gates.

The next generation (CMOS) used about the same area -- you need at least a transistor and resistor, for an NMOS gate cell -- but the resistors get replaced by PMOS, making it much more powerful.  There isn't anything wrong with making dynamic gates in CMOS still, but they probably used it as a selling point, or maybe there were, say, knock-on fab benefits that I'm not aware of.  The onward march to finer feature size helps too, although I don't know that, say, nearby generation NMOS and CMOS Z80s, were very different?

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Offline alank2Topic starter

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I am thinking specifically of the Z80 - the documentation talks about CMOS versions being static, but not the NMOS.
 

Offline tsman

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I am thinking specifically of the Z80 - the documentation talks about CMOS versions being static, but not the NMOS.
The documentation is referring to the original NMOS design which had a minimum clock speed and the later improved CMOS designs which had no minimum and a much higher maximum. The minimum clock speed requirement is just down to how Zilog designed the original NMOS version.
 

Offline iMo

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The most old NMOS CPUs were using "dynamic" cells in their logic in order to simplify their design. The dynamic cell or logic component consists of a small value capacitor (like dram memories) which when charged does a logic operation A, when discharged op B.
While the capacitor discharges itself slowly (leakage currents), you have to refresh it quite often such it does not change the logic state. Therefore the "minimal" clock frequency.
Readers discretion is advised..
 

Online coppice

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I am thinking specifically of the Z80 - the documentation talks about CMOS versions being static, but not the NMOS.
If you can stop and start the CPU clock, you can be pretty sure the entire chip uses static logic. Many NMOS devices were like this. When the device contains some dynamic logic they will specify a lower bound for the clock frequency, which is typically 5% to 10% of the maximum. This clock is needed to keep pumping the dynamic logic. Many NMOS devices were like this. Dynamic logic had speed and power advantages, but can be less robust. Devices for high reliability applications were always statically designed.

Try looking at the specified clock speed range for some old NMOS parts. Some have a lower bound and some don't. Be careful, because in some data sheets the lower bound is not explicitly stated. It has to be inferred from a specified maximum duration for the clock being high or low. The original Z80 is an example of a dynamic device with a specified lower clock bound. If you look at other devices from that era, many have no lower clock bound.
 

Offline alank2Topic starter

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Ok, so what is dynamic logic????
 

Offline tsman

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Ok, so what is dynamic logic????
imo briefly explained it above. Wikipedia has a longer explanation.

Quote
It is distinguished from the so-called static logic by exploiting temporary storage of information in stray and gate capacitances.
 

Online SiliconWizard

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