Curious voltage inverter behavior when under load

[LoveLaika]

I built a power supply. It takes a DC voltage in and outputs a positive and negative voltage. The positive voltage is generated via a buck converter; the negative voltage is generated with a buck-boost inverter. Both run off of the LT1765 IC. I'm having a strange issue with the circuit, and I was wondering if I could get some help troubleshooting it.

At a high level, the circuit works by taking an input voltage (in this case, a bench power supply). It goes through a reverse voltage protection circuit (to prevent any reverse connections), and a slow starter PMOS circuit prevents inrush by limiting the current that goes to the input capacitors until a certain amount of time (handled by the NMOS and gate capacitor). From there, under-voltage lock out circuits prevent the ICs from working until the input voltage reaches a certain level. Once reached, the ICs work, generating their output voltages, while a BJT slow starter circuit adds some delay on the output voltage.

I built the circuit twice on a PCB board. The first time, it works fine with a 20-ohm load on both outputs. Both circuits maintained their voltage (+10 and -10 V) while outputting 500 mA. That's good. However, my second board had some issues. When I hooked the same resistive load to the negative output, the negative voltage was not maintained, dropping down to ~-3.6 volts. That seemed odd. I see the correct output voltages when there's no load, but when I power it on with a load attached, the negative voltage shows that issue. The positive voltage regulator worked in my tests. I always saw that it was outputting the correct voltage when a load was attached to it (+10 volts, 20-ohm load).

I troubleshooted the circuit, and I found that the problem was with the negative voltage regulator's BJT slow starter. Removing the slow starter (by removing the capacitors used in it) seemed to make it work....sometimes. Whenever I power on the bench supply, sometimes I see the correct negative voltage while the load is attached (-10 volts, 20-ohm power resistor). Other times, it's not maintained, and that voltage-dropping issue occurs. Why would this be occurring intermittently? Nothing is shorted, and following my circuit, everything should work. I just don't get why this would happen.

[thm_w]

- Was there a reason for adding 330pF capacitor on the feedback dividers?
- Try bypassing the softstart/reverse and power the IC directly, does anything change?
- Do you have an oscilloscope to look at the FB pin, etc?

[LoveLaika]

Thanks for your reply. If I may, I'll try and respond as best as I can.

1. Admittedly, this was something I took from another design. Following an older design that used the LM25956, that cap on the feedback divider is a feedforward capacitor to help assist in the feedback loop by increasing the phase margin for better loop stability. I thought it would benefit this design as well.

2. I tried out what you suggested. By removing my 15-ohm resistor, PMOS U4, and C37 (1 uF) and connecting a lead to the POS_REG_IN, I was able to bypass my inrush current limiting circuit and power the ICs directly straight from my bench power supply. Interestingly enough, it works. I was able to power on the bench supply and have the correct positive and negative output voltages, even when there was a heavy load connected (20-ohm on each side). I suppose this is the most telling.

3. Yes, I can observe certain points on the board with an oscilloscope. I haven't done that yet given the results of the test above.


EDIT: What a curious side effect. So, as of this post, it's been determined that the circuit works while there's a load attached by doing the following:

• Bypass the inrush current limiting circuit and reverse voltage protection (remove R15, C37, and PMOS U4)
• Bypass the negative slow starter by removing the capacitor(s) linked to it (from the picture, removing C8)
• Powering the ICs directly by connecting a wire to the POS_REG_IN node and powering it on from there

I noticed another curious side effect while the negative circuit was under load. There was some strange noise coming from either the negative voltage IC or its associated inductor (or at least something on that side of the board). I heard something akin to high-frequency whining that dies after a little time. That sounds like an indication of something, but I don't know what that would be. For what it is worth, my inductor is one of those shielded fixed power inductors (10 uH, 10-amp rating). I only heard this recently. It's odd as to why this didn't happen in my first board but only in my second one, despite me making sure that all components were within their rated values.

EDIT 2: Ok...this feels a bit odd...so, after the aforementioned test, I wanted to see what would happen if I put the PMOS and R15 back (but not C37 or the negative slow starter). Would it still behave as the last test, or would it crash and burn? After putting them back, I powered it on, and the voltage still dropped under load, staying at a constant -3 volts. Sure, I should have predicted that. But, I wanted to make sure. Just on a whim, I tried something with my bench supply. The supply I'm using is a dual output supply, capable of having 3 amps on each output. So far, I've been trying it with one output at 3 amps max. However, on this whim, I put the outputs in parallel mode, essentially combining the outputs together so there's one output voltage, but the current capability is doubled to 6 amps. Now, with the PMOS and resistor still soldered onto the board, I powered on my bench supply in this mode allowing for current to be drawn. There is a 20-ohm load attached to the negative output. Interestingly enough, the negative output voltage didn't stay at -3 volts as how it behaved before, but I used a multimeter and observed it climbing to -5 volts and more. On top of that, there was some high-frequency whining. The whining noise grew as the voltage went to -10 volts, then it kind of stayed stable before dying. And there's no slow starter circuit. It sounds like the whining is a sign that perhaps something on the negative side is struggling. 

EDIT 3: ....So, for the second edit, I think I found the cause of the high pitch whining. I accidentally put 26 volts instead of 13 volts to the board. Fried my negative voltage IC. I replaced it and it's back to the last known state: still not outputting the correct voltage under a 20-ohm load. So, using an oscilloscope, I measured the output voltage and the feedback voltage. They more or less follow the same pattern. It starts at 0, rises up to ~250 mV for a few milliseconds, but then it drops to the corresponding set voltage. Without a load, the output voltage was -10 volts while the feedback voltage was around -8.74 volts. That's roughly 1.25 volts in between the the output and the feedback (which I suppose makes sense since the output is taken at the IC's ground pin). This same behavior also occurs with a load, though the voltages are wrong.

So, I had a look at the input voltage. When the bench supply is powered on, the voltage rises from 0. But, when it reaches ~8.7 volts, the voltage drops suddenly to ~1.50 volts. After that, it rises again to the established voltage of 13.7 volts, or whatever voltage the bench is set for. It's rather noisy. I think the drop might be the result of the negative voltage regulator working, as the negative output is tied to the opposite end of its respective input caps.

[thm_w]

The datasheet schematic does not include those capacitors so I would be tempted to leave them off to begin with unless there was a specific need for them, or if you had measured the impulse response and wanted to tweak it. But hopefully unrelated to the issues here.

Is the inrush circuitry necessary? What is the intended power source and why can it not handle supplying ~220uF of input capacitance?
If it can't note that datasheet only uses 2.2uF for LT1765 input, so, maybe you could get away with less depending on your application.

See if you can do a long scope capture of the IC starting up.

[LoveLaika]

Thanks. I'll see what I can do about the scope capture. Hopefully that'll give a better idea of the startup sequence than words alone.

For the moment, I think those feedback caps are unrelated to the issue. Removing them still didn't help matters.

In the first power supply that I made (call it version 1), it drew too much current at startup, more than what a regular supply could handle (~4 amps). For version 2.0, I added the inrush current limiting circuit so it can be used with smaller, less capable supplies. Right now, I'm testing it with my dual supply, with each output capable of 3 amps (or 6 amps when you parallel the supplies through its voltage tracking mode). As a small test, I tried removing the 100 uF caps at the input with the same results.

[temperance]

I think the problem is how this circuit starts.

The SHDN sees 1.33 V when Vin reaches about 9 V but the inrush current limiter is not being driven into saturation at that moment.

I would remove the inrush current limiter or make sure the regulators can't power up before the inrush current limiter is driven into saturation.

EDIT: the inrush current limiter also goes out of saturation when the input voltage changes. I think that's not what you want.

[thm_w]

Oh you didn't have to remove the caps, was just curious why the inrush circuitry was implemented in the first place, if you had some source that can't handle capacitance.

I would have expected the soft start circuitry you implemented on the outputs to slow the conversion down enough to limit input current sufficiently. Maybe it can be even slower if your load is OK with such a slow start up (obviously resistive load won't have an issue).

Under normal startup (without the slow start) I guess 4-8A is not unexpected based on the converter, and no external sense resistor to tweak that.
But if this is automotive, a car battery will easily give you 8A.

[LoveLaika]

Thanks for your response. The power source is not something like a car battery. A slow startup isn't the issue, but a wrong startup while a load is attached is. My load won't draw a lot of current, but I just used a typical 20-ohm load to prepare for the worst case scenario.

I've managed to run some tests and obtain some waveforms. I've attached some pictures showing the startup of my circuit in various scenarios to better illustrate what I'm seeing. I also uploaded some excel files of the more cleaner waveforms. If you need more excel files of scenarios, please let me know which ones would help.

To briefly summarize, the images show the IC's power input pin (yellow), the negative output voltage (blue), and the negative feedback pin (pink). The three scenarios show the traces when there is no-load, when the output voltage is incorrect under a 20-ohm load, and when the output is correct under the same 20-ohm load. I have it for when I power the ICs directly and bypassing the inrush limiter (labeled as DIRECT_POWER) and when I power the ICs passing through my inrush limiter (labeled as SCH_POWER). I hope that this labeling is not too confusing. I tried to label them as such in the excel files. Please note that the positive output regulator has no load; only the negative output regulator is loaded with 20-ohms.

As you can see, passing the voltage through the inrush limiter really cleans up the voltage signal. Unfortunately, that doesn't bode well for the pictures showing the direct power, especially while under load. What I'm curious about is the comparison of the pictures under no-load and showing the correct output. As the input voltage reached the peak (set for ~+12 V), there's a slight dip somehow for a few milliseconds. On the other hand, looking at the bad output, that little dip doesn't appear and the output voltage is all wrong. You would think that it would be the opposite way. I don't see why this would be indicative of the correct output showing up. Perhaps it might have something to do with the input capacitor somehow.

[LoveLaika]

I think the problem is how this circuit starts.

The SHDN sees 1.33 V when Vin reaches about 9 V but the inrush current limiter is not being driven into saturation at that moment.

I would remove the inrush current limiter or make sure the regulators can't power up before the inrush current limiter is driven into saturation.

EDIT: the inrush current limiter also goes out of saturation when the input voltage changes. I think that's not what you want.

Thanks for replying, but it doesn't make sense. Looking at the pictures in the post below, the results still stay the same whether I power the circuit directly (bypassing the resistor and the PMOS) or whether I power it my intended way (going through the reverse-voltage protection PMOS and the inrush current PMOS). Since you suggested the idea of the PMOS not being drawn into saturation, I tried removing the Zener diodes to try and see if it would make a difference (perhaps they were causing the circuit to not get the right voltages and drive it into linear mode or cutoff). It didn't make a difference. The only thing that I can see that's different between when the circuit actually worked and when it didn't was a drop in the voltage trace that's powering the ICs. You can see it in the pictures I've attached showing the input voltage (yellow), the positive regulator output (blue), and the negative output regulator (pink). Funny, I don't even know how this is occurring.

I keep trying some different tests to see how this condition occurs (try to soft start one regulator and leave the other one untouched; increase the input/output capacitance leaving the other untouched; have the inrush current slow start time be very slow), but I don't understand why this occurs. I simulated the circuit a lot, and it didn't show any problems. The output voltages rose (or fell) to the correct levels.

[moffy]

All of your input filter caps on the negative supply go through the load to ground. On the datasheet: https://www.analog.com/media/en/technical-documentation/data-sheets/1765fd.pdf page 17 figure 12 they show the major capacity of the input caps is connected to ground directly and only 2.2uF connected from input to output.

[LoveLaika]

So this would be an issue with the load, acting as a "short" of sorts leading the input caps to ground? The whole purpose of using a simple load like that was to test the capabilities of this buck-boost inverter. Sure, realistically, a real-life load would have capacitance and such, but this was just for testing.

I tried removing my big 100 uF caps at the input, but it still didn't help. Even removing the 10 uF at the negative IC's input (leaving only ~1.1 uF between VIN and NEG_OUT) still didn't make a difference. Since the input voltage node is shared by both ICs, wouldn't the negative IC input still see the other capacitors that go to ground at the positive IC's side?

[moffy]

Since the input voltage node is shared by both ICs, wouldn't the negative IC input still see the other capacitors that go to ground at the positive IC's side?

Yes they would but proximity is always an issue, having caps to ground right next to the ic is not the same as having them some distance from the ic, not saying it will do anything but it is a difference between your design and the recommended. If there is no good reason to change I would go with the recommended.

[LoveLaika]

To be fair, I made these changes in the simulation to reduce the output's noise. It worked in simulation, and it worked on my first board. I just don't know what went wrong with this second one (and this third one I made as well).

I made a bit of a drastic change and tried removing all the 100 uF caps from my circuit to try and keep it simple. I also added 20 uF from the input to ground to follow the recommendation, but it still didn't work. It doesn't seem to be the slow starter or the inrush current limiter. It's so odd. The only thing that seemed constant was that when the correct voltage was reached when connected to a 20-ohm load at startup, the input voltage "dropped" a bit as shown in the circle in the picture. I don't know why this happens, and I can't seem to replicate it. Every time I run the circuit now, I can't get this to happen, and the negative output voltage stays low at -3 volts or so.

For what it's worth, I've tested my circuit while connecting the negative output to a 30-ohm load, and the output voltage was correct at -10 volts (though I did shut it off early cause the resistor got hot). I also tried to "hot plug" the 20-ohm load after startup, and the power supply did output 500 mA at -10 volts. It's only at startup that this situation occurs.

[moffy]

A good fault finding process would be to build just the negative supply with the 20R load as per the recommended datasheet, test, then add a feature test again until it doesn't start up properly. Go from working simple to more complex in steps, systematic and hopefully definitive.

[LoveLaika]

Running some more tests, it appears that (with my current configuration) my PMOS is not going into saturation at all. Rather, it appears to be in linear mode. Here, let me show you.

The pictures show four traces in this order: the power supply (yellow), the PMOS gate (light blue), the PMOS drain (pink), and the PMOS source (dark blue). The math trace (M on the left side) shows either Vsd (source-drain) or Vsd (source-gate). The PMOS has three stages: cutoff (Vsg < |Vtp|), linear (Vsg> |Vtp| and Vsg > Vsd), and saturation (Vsg> |Vtp| and Vsg < Vsd). I tried to scale the images below to better show the traces, but from the math trace, it seems that Vsg is always larger than Vsd. The RSJ250P10 has a gate threshold voltage between (-1.0) and (-2.5) V. Vsd seems rather low, close to 0, while Vsg rises accordingly. From the way it behaves, it seems that Vsg is always in linear mode since it's greater than Vsd.

For my parameters, at this point in time, the soft starter had a 0.1 uF cap to delay the NMOS (M1 in my schematic). U1 only has 11.1 uF capacitors at the input and output, while U2 has 2.1 uF connecting Vin to the negative output (not shown, but there's also 20 uF from U2's Vin to ground closer to the IC). There are no 100 uF caps currently on my board for testing. This behavior makes sense, as the PMOS acts as a low resistance path ideally from the power supply to the IC's VIN. So, drain and source should be the same and the PMOS should behave linearly.

[LoveLaika]

After some testing, I found something that made a difference. You can see in the pictures above.

It was the capacitor between the PMOS's gate and drain that resulted in the changes below. In the four images, you see the negative voltage output (yellow), the PMOS's Gate (light blue), PMOS Drain (purple), and PMOS Source (dark blue). For the purposes of this test, I removed both UVLO of the regulators by leaving the pin open (removing resistors and the cap connected to it). The inrush NMOS cap is 1.2 uF while both slow starters have 0.1 uF caps. Rather than have both UVLO and regulator slow starter, I rather go with the slow starter.

You can see how the circuit behaves on startup. Voltage starts building up, but when it reaches ~2.9 or 3 volts, the drain voltage decreases to ~2 volts. I'm guessing that this is because the regulators start to turn on. However, the gate also drops too as you can see. With the way it is, the PMOS is in linear mode for a while until the positive output and negative output increase/decrease respectively. At that point, close to the center of the image, drain and source voltage match while the gate voltage also increases. Here, I'd say the PMOS is fully on.

Without the drain-gate cap, the negative output can decrease when there's no load. However, when there is a 20-ohm load, for some reason, the negative voltage fails to reach the preset output voltage. It gets stuck at ~-3 volts or so. Interestingly enough, having a load also affects the time the PMOS spends in linear mode when you compare the two pictures.

Now, when you add a capacitor (1 uF; I tried with 0.1 uF, but it was too small), at the same time when the output voltages increase/decrease, the gate voltage suddenly follows drain and source for a few milliseconds before dropping (which turns on the PMOS). I find this to be particularly interesting, because in this case, the output voltage did manage to reach its correct voltage value. Hopefully, this whole incident might be a result of UVLO combined with that capacitor, but I wonder why this circuit would behave this way with the capacitor? You can see in the close up picture that the drain voltage is lower than the gate voltage at one point, so could it be going into saturation during this time? Could the capacitor be trying to resist the change in voltage between the gate and drain when the regulator input voltage changes?