Current ranger schematic

[fedimakni]

Hello,
I am planning to make the current ranger made by lowpowerlab but i really didn't get something concerning his schematic:
- Why using all p-channel mosfet in the schematic when he could simply use one n channel mosfet and switch it off and on when needed as dave mentioned in his videos (designing a better multimeter) ?
- The leakage current of the mosfet is around 1uA so doesn't it affect the accuracy of the measurement even if it's off?
- why he doesn't use a mosfet for the nA range too and keep it on all the time?
-Is there any purpose for the GND-ISO? could I not wire it to the microcontroller and keep working normally with it?
- Does it make any difference if cascading resistors as dave make in his video designing a better multimeter or leave it in parallel?

I will be very thankful if I get some answers for my questions. Please cooperate and thank you very much.

[wraper]

- Why using all p-channel mosfet in the schematic when he could simply use one n channel mosfet and switch it off and on when needed as dave mentioned in his videos (designing a better multimeter) ?

Probably to decrease leakage current by driving MOFET gate with positive voltage when it's closed

- The leakage current of the mosfet is around 1uA so doesn't it affect the accuracy of the measurement even if it's off?

Did you just randomly pull out this figure? I doubt it's this high and also depends on particular MOSFET, Vgs, Vds, temperature.

- why he doesn't use a mosfet for the nA range too and keep it on all the time?

Because it does not affect a measurement to a large enough degree to bother. In uCurrent 10k resistor is permanently connected too.

[fedimakni]

Thanks for the answers.
Just one last question if that doesn't bother you:
-Does it make any difference if cascading resistors as dave make in his video designing a better multimeter or leave it in parallel?

Regarding the leakage current some other post about current ranger mentioned that he used IRLML5203 which has 1uA leakage current, Do that really affect the measurement if it's that high?

[wraper]

he used IRLML5203 which has 1uA leakage current

This is max spec at 24V Vds. Also for 10 mOhm resistor there should be a much beefier MOSFET, otherwise MOSFET will cause 10 times more burden voltage than the shunt itself. Not that I'm saying this circuit is all good and actually adheres to its specifications.

-Does it make any difference if cascading resistors as dave make in his video designing a better multimeter or leave it in parallel?

If it's a standalone device like multimeter, it does not matter at all. Even if it's not individually calibrated, it can be dealt with in firmware. If it's not, it can be dealt with by slightly adjusting a gain of op-amp.

[Kleinstein]

I don't see a real advantage in using P MOSFETs. The logic is different, but nothing really different. Usually same size n FETs have a lower on resistance.  At least from the normal specs the leakage current of P-FETs is not significant lower than with n channel fets. There still may be lower leakage - this would be the only sensible reason.

The parallel configuration results in nice simple resistor values.
The series configuration gives slightly odd values, but can get away with less FETs.

[fedimakni]

Hello,

How it results in less fet? I think they will use the same number of fet in parallel or series configuration.

[Kleinstein]

The parallel configuration needs an extra FET for sensing the voltage. So ideally one needs 2 Fets for every Shunt. For lower accuracy (e.g. 4 digits) one can do shot cuts like in the circuit shown, with the larges resistor always in parallel, that can save a switch. As a second approximation the circuit as shown has the on resistance in series to the 10 Ohms shunt without correction. So the circuit as shown gets away with 4 FET switches (the rest of the switches are logic , level shifting).
Still this is only an approximation with some residual effect of the FETs on resistance.

The shunts in series configuration only needs 1 switch for every shunt, as the voltage is always sensed the same way (from the lowest current shunt). There is a small downside however: leakage at the highest shunt can also effect the high current ranges.  So for the highest resolution one may still want to switch the voltage sensing point ( have an extra fet in parallel to the largest shunt). However the FETs in question are small and voltage is low, so the error can be quite small. So the simple form with 3 shunts would need only 3 FET switches and only one of these would need to be low R_on.

The circuit as show has more trouble: The protection at the input is not working well (the diode at the input should be the other way around - the other direction is already through the FETs). The 2 transistor at the in input would only limit the voltage to some +-8 V - so long after the rest has failed. There is also a floating "GND-ISO" - this needs to be at a defined level to make the switching work.  So the comment on simply connecting it is very valid. One may want it at some value a little higher than the µC GND, so the µC could also read the output.

[exe]

2Kleinstein: is this the circuit you mean?

[fedimakni]

So do you think such a device could be an easy alternative to the current ranger?
The same mechanism but n channel mosfet controlled from a raspberry pi.

[Kleinstein]

The circuit shown has the FET also in series with the lowest level shunt. This can cause quite some errors, as the R_on is no longer much smaller than the shunt. If using a very large low R_on FET this will have more leakage, effecting the small current range. The 10 mOhms shunts have 4 wire contacts for a good reason - so one should use them.

There is another problem with this circuit: when going for low burden voltage, there is not that much dynamic range left. So shunt in 10 K  10 Ohms, and 10 mOhms are spaced quite far apart. Even the AZ OPs have trouble much below 1 µV. So one would have some 2 digit resolution with 0.1 mV at the shunt - just before the next shunt is available one would have 100 mV than. The simple switching with just 1 FET is limited to low burden, because of the parasitic diodes - so already 100 mV may cause trouble from leakage at the large FETs in reverse direction.
Especially with low burden it would like more ranges, more like 10 K, 100, 1,  10 m.

The rasberry circuit is more like a good source for EMI, not so desirable for a precision circuit. Switching ranges would be more like something for an Arduino or similar class µC. It can help to have 5 V level for the switching to get low R_on and low leakage. So the FETs could see something like +3-4 V when on and -1 .. -2 V when off. Low level MOSFETs tend to be slightly higher leakage.

Attached is a rough sketch of a possible input. The FET types are not the ideal choice, just a crude selection of what I had in the libs.  The 2 MOSFETs back to back can help, but it depends on the details and which part is more important.

[neutrino353]

I am planning to make the current ranger made by lowpowerlab but i really didn't get something concerning his schematic:

Hi, how is it going on making the current ranger ? I am considering design and make a stuff with similar functionality as the current ranger, and want to learn and understanding more
before start making it. The schematic of the current ranger post on its own site is a bit confusing. Some of the questions I originally have , has been answered in this post (thanks a lot).
Just want to know the current progress of your project.

[fedimakni]

Hello,

I actually used the same mechanism as dave mentioned in his video ( designing a better multimeter ) cascading 3 resistor and using n channel mosfet and it works fine for me. The only drawbacks maybe is that you should use a low side measurement with negative pin directly connected to ground. But it works for me.

I hope that it helps you

[neutrino353]

Thanks for your info. Will read and borrow any idea that is applicable to my design.

[EEVblog]

Why wouldn't you just use this?
I don't get why leakage would be a problem with a 10k max shunt impedance.

[fedimakni]

Hello Dave,

Actually i used the same topology and it works perfectly fine for me thanks. I made a choice of CSD16321Q5 as mosfet
Datasheet: https://www.ti.com/lit/ds/symlink/csd16321q5.pdf?ts=1595942573750&ref_url=https%253A%252F%252Fwww.google.com%252F
it works great for me after that i used ADS1115 to feed data to uC and until now everything is great.
Thank you again for all the experience you gave us. 

[neutrino353]

I've thought of using this method, but if use this and when measuring using the 10m Ohm range, will the voltage reading goes into the opamp include the voltage drop due to
the mosfet's internal resistance ?

[Kleinstein]

The circuit is missing the other side terminal for the current and another FET to separate the 10 K Shunt. Than the drop on the MOSFET for the 10 mOhms shunt would not be included.
With only one MOSFET the burden voltage including the drop at the FET should be small (e.g. < 100 mV), as there is always the parasitic diode with the FETs.

[neutrino353]

Actually i used the same topology and it works perfectly fine for me thanks. I made a choice of CSD16321Q5 as mosfet

Your choice of CSD16321Q5 has much lower on-resistance than the FDS8984 that I've currently chosen !!! Seriously consider to change using it. Thanks.
(The most time consuming task in design a circuit is choosing the right component)

[Kleinstein]

Very low R_on comes with the downside of more leakage. This may be a problem, especially for the FET not shown in the circuit. 1 type of FETs for all switches is not the best solution, one may need 2 types.

[neutrino353]

The circuit is missing the other side terminal for the current and another FET to separate the 10 K Shunt. Than the drop on the MOSFET for the 10 mOhms shunt would not be included.
With only one MOSFET the burden voltage including the drop at the FET should be small (e.g. < 100 mV), as there is always the parasitic diode with the FETs.

Could you show me in detail how to do this ? One of the reason I don't use current ranger's circuit and do my own design is that it includes the Fet voltage drop in the 10 mOhm
mode sampling.

[Kleinstein]

The circuit is missing the other side terminal for the current and another FET to separate the 10 K Shunt. Than the drop on the MOSFET for the 10 mOhms shunt would not be included.
With only one MOSFET the burden voltage including the drop at the FET should be small (e.g. < 100 mV), as there is always the parasitic diode with the FETs.

Could you show me in detail how to do this ? One of the reason I don't use current ranger's circuit and do my own design is that it includes the Fet voltage drop in the 10 mOhm
mode sampling.

I have shown the circuit principle before. The circuit there is a little more complicated with an extra 4 th channel using an TIA and the extra input protection, so that one would not burn the shunts so easy.  Depending on the burden one may get away without the 2 fets in series.

[EEVblog]

The circuit is missing the other side terminal for the current and another FET to separate the 10 K Shunt.

Not needed, the 10k is permanently in parallel, just like on the present design uCurrent.

[neutrino353]

The circuit is missing the other side terminal for the current and another FET to separate the 10 K Shunt. Than the drop on the MOSFET for the 10 mOhms shunt would not be included.
With only one MOSFET the burden voltage including the drop at the FET should be small (e.g. < 100 mV), as there is always the parasitic diode with the FETs.

Could you show me in detail how to do this ? One of the reason I don't use current ranger's circuit and do my own design is that it includes the Fet voltage drop in the 10 mOhm
mode sampling.

I have shown the circuit principle before. The circuit there is a little more complicated with an extra 4 th channel using an TIA and the extra input protection, so that one would not burn the shunts so easy.  Depending on the burden one may get away without the 2 fets in series.

Actually I am using sensing resistors in series in my design but cannot get rid of the FET voltage drop.

Thanks very much that I found your post about your proposed circuit for the current ranger. Your extra FET for the 10K resister solve the "FET voltage drop issue", but require that  the  opamp have very very little bias current so that the current drop across that 10K resistor  can be ignored.
I've do a simulation on Ltspice using FDS6670A mosfet and LTC2050HV opamp  and the result is very satisfactory.

Also , I will add one more shunt stage with ratio 1 : 100 : 10000 : 1000000 to ensure the entire range will have at least 3  digit (0.01 %) accuracy.

There are still to question I don't understand in your proposed circuit :-

1) What is the different of a 4 wire resistance to a normal 2 terminal current sense resistor ?
2) Why using 2 mosfet in series instead of just one when connect the 10mOhm shunt resister to the current source terminal ?

[EEVblog]

1) What is the different of a 4 wire resistance to a normal 2 terminal current sense resistor ?
2) Why using 2 mosfet in series instead of just one when connect the 10mOhm shunt resister to the current source terminal ?

1) It's potentially more accurate. 4 terminal measurement is standard practice in the low ohm world. And the good current shunts down in that range are 4 terminal.

2) Sorry, I did not draw the top + input. They are not in series, they are in parallel. Having the 10R come from the tap of the 0.01R removes the FET voltage drop from the reading.

[prasimix]

4-wire or Kelvin connection can be emulated on the PCB with 2-wire sense resistor (see picture).
I would warmly recommend the ROHM resistors of the GRM100 series (e.g. GMR100HTBFA10L0 for 10 Milioms). So far I have not found anything similar in that price range with TCR of only 20 ppm! It's simply excellent as advertised.

[Kleinstein]

Daves circuit does include the FET on resistance for the 10 mOhms resistor - voltage is sensed directly from the input - the 10 Ohms in parallel to the FET does not make a lot of difference.

2 Fets in series helps with leakage currents if the voltage gets a little larger (like > 100 mV), as there is the parasitic diode that would be forward biased in one direction. Not so sure of the 2 fets are more needed with the large fets for the high current, or more with the smaller ones for the low currents.

The 10 K shunt in series with the sensing circuit can indeed be a weak point. One point is the bias from the OP: some 10 pA * 10 K  is some 100 nV, so with the max4239 / LTC2050 this is not yet that dramatic. The other point could be added noise - though not yet much compared to the max4239 or similar. The series connection gets problematic with even larger shunts. Even instead of a 10 K shunt the TIA version may be favorable.

[EEVblog]

Daves circuit does include the FET on resistance for the 10 mOhms resistor - voltage is sensed directly from the input - the 10 Ohms in parallel to the FET does not make a lot of difference.

The FET on resistance is not included in the actual measured shunt resistance though. But of course you can't avoid it in the total burden voltage.

[EEVblog]

4-wire or Kelvin connection can be emulated on the PCB with 2-wire sense resistor (see picture).
I would warmly recommend the ROHM resistors of the GRM100 series (e.g. GMR100HTBFA10L0 for 10 Milioms). So far I have not found anything similar in that price range with TCR of only 20 ppm! It's simply excellent as advertised.

Only 1% though.

[prasimix]

4-wire or Kelvin connection can be emulated on the PCB with 2-wire sense resistor (see picture).
I would warmly recommend the ROHM resistors of the GRM100 series (e.g. GMR100HTBFA10L0 for 10 Milioms). So far I have not found anything similar in that price range with TCR of only 20 ppm! It's simply excellent as advertised.

Only 1% though.

Not really a problem if you count on calibration, otherwise yes, a better tolerance is more welcome.

[neutrino353]

1) What is the different of a 4 wire resistance to a normal 2 terminal current sense resistor ?
2) Why using 2 mosfet in series instead of just one when connect the 10mOhm shunt resister to the current source terminal ?

1) It's potentially more accurate. 4 terminal measurement is standard practice in the low ohm world. And the good current shunts down in that range are 4 terminal.

2) Sorry, I did not draw the top + input. They are not in series, they are in parallel. Having the 10R come from the tap of the 0.01R removes the FET voltage drop from the reading.

1) noted with thanks.  I don't have 4 wire sensing resistors, but will emulate the Kelvin connection on the PCB
2) not quite understand your circuit , but add a mosfet before the current source and the largest shunt resistor does eliminate the FET voltage drop issue.

[EEVblog]

2) not quite understand your circuit , but add a mosfet before the current source and the largest shunt resistor does eliminate the FET voltage drop issue.

You cannot avoid the FET voltage drop adding to the burden voltage, that simply isn't possible.

[Kleinstein]

With only 2 switches (FETs) and 3 shunts one would have the drop from the FET also with the lowest shunt. The voltage sense would not be through the 10 and 10 K resistors, but the direct way on the top. So the 3 rd Fet is required.

[EEVblog]

With only 2 switches (FETs) and 3 shunts one would have the drop from the FET also with the lowest shunt. The voltage sense would not be through the 10 and 10 K resistors, but the direct way on the top. So the 3 rd Fet is required.

Complete brain fart 
Yes, 3rd FET required on the 10k.

[neutrino353]

2) not quite understand your circuit , but add a mosfet before the current source and the largest shunt resistor does eliminate the FET voltage drop issue.

You cannot avoid the FET voltage drop adding to the burden voltage, that simply isn't possible.

I am not trying to get rid of the FET voltage drop. I just want to have a circuit that the opamp don't include the FET voltage drop during measurement.

Attached is analog part of my circuit ( not finalized). It run very well in the Ltspice simulator. Will verify it on breadboard when the require parts arrived

[Kleinstein]

The principle circuit looks OK. However the choice of shunt resistors is a little odd: 8 and 80 Ohms are quite close together, while 80 to 80 K is a large step.
The other point is that 80 K is quite a large value and thus leakage current at M3 can be critical.
Chances are one could find a lower leakage fet.
For the largest resistor one may consider a switch directly in parallel and having that switch effectively in series with the next larger shunt. With some 80 (or 800) Ohms this may not be so bad.

[neutrino353]

The principle circuit looks OK. However the choice of shunt resistors is a little odd: 8 and 80 Ohms are quite close together, while 80 to 80 K is a large step.
The other point is that 80 K is quite a large value and thus leakage current at M3 can be critical.
Chances are one could find a lower leakage fet.
For the largest resistor one may consider a switch directly in parallel and having that switch effectively in series with the next larger shunt. With some 80 (or 800) Ohms this may not be so bad.

I make a mistake.  The 80ohm resistor should be 800 ohm,  making each shunt has a ratio  of 1:100. This values in not final as i have to compremise between the reading range . Voltage drop and accuracy.

For the shunt of 80k,  i choose the RHK005N03 mosfet (  just a quick pick from ltspice's available list)  which has higher on-resistance but low leakage current.

My target is to have a maximum voltage drop of 0.1v within the 1nA to 1000mA range.  I have chose the mcp3426 16 bit Adc to get the voltage reading.  mcp3426 is 15bit , mean that the resolution for the opamp input is 0.1v / 32768  ~= 3uV. The accuracy i expect is +/- 0.05% (actually 0.1% is more than enough for my purpose) 

[Kleinstein]

With 0.1 V of voltage drop the MOSFETs may have a significant leakage when the parasitic diode is in forward direction. So I am a bit skeptical if this would work with 80 K, it may work with some 10 K or so.

The leakage can be via 2 paths:
1) through the large fet, so that the low current range could read a little low.
2) through the small fet, loading the sense line with the 80 K in series. This would especially effect the highest current range. Here it is the drop at the shunt, but the drop at the fet. So the fet for the highest current range should not be too small. So this case may be OK and not so critical, as the voltage can be smaller.
It is still a tricky balance between low leakage and low R_on.
For less leakage in the off case one may use a slightly negative gate voltage, especially with low threshold fets.

Another point to watch would be some protection against overload. This would be mainly the 8 Ohms shunt, that could burn from too much current (e.g. > some 500 mA)

AFAIK the MCP3426 and similar ADCs have the option to use internal gain. This gain is quite stable and could be helpful. Unless one needs a fast result on should be able to go below 3 µV resolution.

[neutrino353]

With 0.1 V of voltage drop the MOSFETs may have a significant leakage when the parasitic diode is in forward direction. So I am a bit skeptical if this would work with 80 K, it may work with some 10 K or so.

The leakage can be via 2 paths:
1) through the large fet, so that the low current range could read a little low.
2) through the small fet, loading the sense line with the 80 K in series. This would especially effect the highest current range. Here it is the drop at the shunt, but the drop at the fet. So the fet for the highest current range should not be too small. So this case may be OK and not so critical, as the voltage can be smaller.
It is still a tricky balance between low leakage and low R_on.
For less leakage in the off case one may use a slightly negative gate voltage, especially with low threshold fets.

Another point to watch would be some protection against overload. This would be mainly the 8 Ohms shunt, that could burn from too much current (e.g. > some 500 mA)

AFAIK the MCP3426 and similar ADCs have the option to use internal gain. This gain is quite stable and could be helpful. Unless one needs a fast result on should be able to go below 3 µV resolution.

I don't have the equipment to measure the leakage current so I have to rely on the simulated result from Ltspice and hope it gives some realistic value.

With the components I've chosen for the simulation.
Scenario 1 :  ~1uA current with M3(80K shunt)  turned on, and the others 3 turned off.
The voltage drop is 0.079 volt. The leakage current through M4(0.08 Ohm shunk) is 90pA, M1 and M2(8 and 800 ohm) is 45pA , giving a total of 180pA
leakage. The % error is 0.18/1000 ~= 0.02% which is better then my target.

Scenerio 2:   ~1000mA current with M4(0.08Ohm) On, other 3 turned off
The leakage current through M3 is ~3pA, the bias current of LTC2050HV is also ~3.5pA,
making a total voltage drop for the 80K + 800 + 8 ohm resisters about 0.5 uV . This is acceptable becauase the minimum resolution of the mcp3426 Adc
with 0.1V full range is about 3uV

If the simulated result is realistic , the circuit should work. Anyway I may reduce the resistance to 50KOhm to 0.05 Ohm to make it capable of measuring
higher current.

I know the mcp3426 has configurable gain of 1x,2x,4x and 8x. So I make the opamp a fixed gain of 10x , giving the output voltage with 0.1V drop at 1V.
This is just less than the full range reading of mcp3426 with 4x gain. I will try to program the uP to switch the gain to read more precise value if the
current drop is far below 0.1v.

Talking about circuit protection, what is the best way to ensure that the maximum voltage difference between the two input terminal will not
exceed say 5v in order not to damage the opamp and the fet ?

[Kleinstein]

The leakage simulation may not be 100% realistic. Leakage can vary between individual units. However the simulation can at least include the diode part reasonably well. So it can be acceptable. Just be warned that leakage can be a problem and the choice of the FETs is no so easy.

For the protection the main danger is overheating of the shunts. So it is about limiting the voltage there. The lowest shunt is usually OK and a simple fuse in series to the input would be enough.
The difficult one is more the 2 nd shunt. One direction it is kind of protected trough the parasitic diode in the MOSFET: it will limit the voltage to some 0.8 V in one direction. With the 8 or 5 Ohms shunt this may be an acceptable power level: 1 V with 5 Ohms would be 200 mW and even some 1.5 V would be only some 500 mW, which could be OK for a shunt that is not too small in form factor.  For the other direction one can add 1 or 2 extra diodes. With 2 diodes one can use an extra OP to reduce the leakage current by reducing the voltage drop over the critical diode, but the maximum voltage is a little higher.

For the OP input just some series resistors would be OK. Most of the OPs can survive some 1-10 mA of current when outside the supplies. The ADC would not be directly exposed to a higher voltage with the OP powered from the same 5 V as the ADC.

[neutrino353]

The leakage simulation may not be 100% realistic. Leakage can vary between individual units. However the simulation can at least include the diode part reasonably well. So it can be acceptable. Just be warned that leakage can be a problem and the choice of the FETs is no so easy.

For the protection the main danger is overheating of the shunts. So it is about limiting the voltage there. The lowest shunt is usually OK and a simple fuse in series to the input would be enough.
The difficult one is more the 2 nd shunt. One direction it is kind of protected trough the parasitic diode in the MOSFET: it will limit the voltage to some 0.8 V in one direction. With the 8 or 5 Ohms shunt this may be an acceptable power level: 1 V with 5 Ohms would be 200 mW and even some 1.5 V would be only some 500 mW, which could be OK for a shunt that is not too small in form factor.  For the other direction one can add 1 or 2 extra diodes. With 2 diodes one can use an extra OP to reduce the leakage current by reducing the voltage drop over the critical diode, but the maximum voltage is a little higher.

For the OP input just some series resistors would be OK. Most of the OPs can survive some 1-10 mA of current when outside the supplies. The ADC would not be directly exposed to a higher voltage with the OP powered from the same 5 V as the ADC.

Thanks for the advise, now I know the key points against over current.
For the over voltage issue, it mostly won't happen as I am aiming at using the device to measure the current usage of some uP with is mostly 3-5v.
So as far as the input voltage is not exceeding the maximum rating of the FET's (~20 - 30v) the circuit is save . Am I correct ?
If I try (just thinking) using this device to measure the current of my tube amp , which is ~230v @ 100 ma , will it blow the device immediately ?

[Kleinstein]

The range switching should be done in a make before brake sequence. So the fets would never see a votlage exceeding about 0.1 V or so. If there are diode(s) for over-current protection the fets may see some 1.5 V in case of over-currents and less than 0.1 V if need exceeding the nominal current. One can still blow the 8 or 5 Ohms resistor with just  5 V.


For use with a high voltage circuit it could be the isolation to the user that matters - the circuit would still only see low voltages.

[farzansaleem]

Hello,
Is it possible for you to share schematic and PCB layout?