Current ranger schematic

[fedimakni]

Hello,
I am planning to make the current ranger made by lowpowerlab but i really didn't get something concerning his schematic:
- Why using all p-channel mosfet in the schematic when he could simply use one n channel mosfet and switch it off and on when needed as dave mentioned in his videos (designing a better multimeter) ?
- The leakage current of the mosfet is around 1uA so doesn't it affect the accuracy of the measurement even if it's off?
- why he doesn't use a mosfet for the nA range too and keep it on all the time?
-Is there any purpose for the GND-ISO? could I not wire it to the microcontroller and keep working normally with it?
- Does it make any difference if cascading resistors as dave make in his video designing a better multimeter or leave it in parallel?

I will be very thankful if I get some answers for my questions. Please cooperate and thank you very much.

[wraper]

- Why using all p-channel mosfet in the schematic when he could simply use one n channel mosfet and switch it off and on when needed as dave mentioned in his videos (designing a better multimeter) ?

Probably to decrease leakage current by driving MOFET gate with positive voltage when it's closed

- The leakage current of the mosfet is around 1uA so doesn't it affect the accuracy of the measurement even if it's off?

Did you just randomly pull out this figure? I doubt it's this high and also depends on particular MOSFET, Vgs, Vds, temperature.

- why he doesn't use a mosfet for the nA range too and keep it on all the time?

Because it does not affect a measurement to a large enough degree to bother. In uCurrent 10k resistor is permanently connected too.

[fedimakni]

Thanks for the answers.
Just one last question if that doesn't bother you:
-Does it make any difference if cascading resistors as dave make in his video designing a better multimeter or leave it in parallel?

Regarding the leakage current some other post about current ranger mentioned that he used IRLML5203 which has 1uA leakage current, Do that really affect the measurement if it's that high?

[wraper]

he used IRLML5203 which has 1uA leakage current

This is max spec at 24V Vds. Also for 10 mOhm resistor there should be a much beefier MOSFET, otherwise MOSFET will cause 10 times more burden voltage than the shunt itself. Not that I'm saying this circuit is all good and actually adheres to its specifications.

-Does it make any difference if cascading resistors as dave make in his video designing a better multimeter or leave it in parallel?

If it's a standalone device like multimeter, it does not matter at all. Even if it's not individually calibrated, it can be dealt with in firmware. If it's not, it can be dealt with by slightly adjusting a gain of op-amp.

[Kleinstein]

I don't see a real advantage in using P MOSFETs. The logic is different, but nothing really different. Usually same size n FETs have a lower on resistance.  At least from the normal specs the leakage current of P-FETs is not significant lower than with n channel fets. There still may be lower leakage - this would be the only sensible reason.

The parallel configuration results in nice simple resistor values.
The series configuration gives slightly odd values, but can get away with less FETs.

[fedimakni]

Hello,

How it results in less fet? I think they will use the same number of fet in parallel or series configuration.

[Kleinstein]

The parallel configuration needs an extra FET for sensing the voltage. So ideally one needs 2 Fets for every Shunt. For lower accuracy (e.g. 4 digits) one can do shot cuts like in the circuit shown, with the larges resistor always in parallel, that can save a switch. As a second approximation the circuit as shown has the on resistance in series to the 10 Ohms shunt without correction. So the circuit as shown gets away with 4 FET switches (the rest of the switches are logic , level shifting).
Still this is only an approximation with some residual effect of the FETs on resistance.

The shunts in series configuration only needs 1 switch for every shunt, as the voltage is always sensed the same way (from the lowest current shunt). There is a small downside however: leakage at the highest shunt can also effect the high current ranges.  So for the highest resolution one may still want to switch the voltage sensing point ( have an extra fet in parallel to the largest shunt). However the FETs in question are small and voltage is low, so the error can be quite small. So the simple form with 3 shunts would need only 3 FET switches and only one of these would need to be low R_on.

The circuit as show has more trouble: The protection at the input is not working well (the diode at the input should be the other way around - the other direction is already through the FETs). The 2 transistor at the in input would only limit the voltage to some +-8 V - so long after the rest has failed. There is also a floating "GND-ISO" - this needs to be at a defined level to make the switching work.  So the comment on simply connecting it is very valid. One may want it at some value a little higher than the µC GND, so the µC could also read the output.

[exe]

2Kleinstein: is this the circuit you mean?

[fedimakni]

So do you think such a device could be an easy alternative to the current ranger?
The same mechanism but n channel mosfet controlled from a raspberry pi.

[Kleinstein]

The circuit shown has the FET also in series with the lowest level shunt. This can cause quite some errors, as the R_on is no longer much smaller than the shunt. If using a very large low R_on FET this will have more leakage, effecting the small current range. The 10 mOhms shunts have 4 wire contacts for a good reason - so one should use them.

There is another problem with this circuit: when going for low burden voltage, there is not that much dynamic range left. So shunt in 10 K  10 Ohms, and 10 mOhms are spaced quite far apart. Even the AZ OPs have trouble much below 1 µV. So one would have some 2 digit resolution with 0.1 mV at the shunt - just before the next shunt is available one would have 100 mV than. The simple switching with just 1 FET is limited to low burden, because of the parasitic diodes - so already 100 mV may cause trouble from leakage at the large FETs in reverse direction.
Especially with low burden it would like more ranges, more like 10 K, 100, 1,  10 m.

The rasberry circuit is more like a good source for EMI, not so desirable for a precision circuit. Switching ranges would be more like something for an Arduino or similar class µC. It can help to have 5 V level for the switching to get low R_on and low leakage. So the FETs could see something like +3-4 V when on and -1 .. -2 V when off. Low level MOSFETs tend to be slightly higher leakage.

Attached is a rough sketch of a possible input. The FET types are not the ideal choice, just a crude selection of what I had in the libs.  The 2 MOSFETs back to back can help, but it depends on the details and which part is more important.

[neutrino353]

I am planning to make the current ranger made by lowpowerlab but i really didn't get something concerning his schematic:

Hi, how is it going on making the current ranger ? I am considering design and make a stuff with similar functionality as the current ranger, and want to learn and understanding more
before start making it. The schematic of the current ranger post on its own site is a bit confusing. Some of the questions I originally have , has been answered in this post (thanks a lot).
Just want to know the current progress of your project.

[fedimakni]

Hello,

I actually used the same mechanism as dave mentioned in his video ( designing a better multimeter ) cascading 3 resistor and using n channel mosfet and it works fine for me. The only drawbacks maybe is that you should use a low side measurement with negative pin directly connected to ground. But it works for me.

I hope that it helps you

[neutrino353]

Thanks for your info. Will read and borrow any idea that is applicable to my design.

[EEVblog]

Why wouldn't you just use this?
I don't get why leakage would be a problem with a 10k max shunt impedance.

[fedimakni]

Hello Dave,

Actually i used the same topology and it works perfectly fine for me thanks. I made a choice of CSD16321Q5 as mosfet
Datasheet: https://www.ti.com/lit/ds/symlink/csd16321q5.pdf?ts=1595942573750&ref_url=https%253A%252F%252Fwww.google.com%252F
it works great for me after that i used ADS1115 to feed data to uC and until now everything is great.
Thank you again for all the experience you gave us. 

[neutrino353]

I've thought of using this method, but if use this and when measuring using the 10m Ohm range, will the voltage reading goes into the opamp include the voltage drop due to
the mosfet's internal resistance ?

[Kleinstein]

The circuit is missing the other side terminal for the current and another FET to separate the 10 K Shunt. Than the drop on the MOSFET for the 10 mOhms shunt would not be included.
With only one MOSFET the burden voltage including the drop at the FET should be small (e.g. < 100 mV), as there is always the parasitic diode with the FETs.

[neutrino353]

Actually i used the same topology and it works perfectly fine for me thanks. I made a choice of CSD16321Q5 as mosfet

Your choice of CSD16321Q5 has much lower on-resistance than the FDS8984 that I've currently chosen !!! Seriously consider to change using it. Thanks.
(The most time consuming task in design a circuit is choosing the right component)

[Kleinstein]

Very low R_on comes with the downside of more leakage. This may be a problem, especially for the FET not shown in the circuit. 1 type of FETs for all switches is not the best solution, one may need 2 types.

[neutrino353]

The circuit is missing the other side terminal for the current and another FET to separate the 10 K Shunt. Than the drop on the MOSFET for the 10 mOhms shunt would not be included.
With only one MOSFET the burden voltage including the drop at the FET should be small (e.g. < 100 mV), as there is always the parasitic diode with the FETs.

Could you show me in detail how to do this ? One of the reason I don't use current ranger's circuit and do my own design is that it includes the Fet voltage drop in the 10 mOhm
mode sampling.

[Kleinstein]

The circuit is missing the other side terminal for the current and another FET to separate the 10 K Shunt. Than the drop on the MOSFET for the 10 mOhms shunt would not be included.
With only one MOSFET the burden voltage including the drop at the FET should be small (e.g. < 100 mV), as there is always the parasitic diode with the FETs.

Could you show me in detail how to do this ? One of the reason I don't use current ranger's circuit and do my own design is that it includes the Fet voltage drop in the 10 mOhm
mode sampling.

I have shown the circuit principle before. The circuit there is a little more complicated with an extra 4 th channel using an TIA and the extra input protection, so that one would not burn the shunts so easy.  Depending on the burden one may get away without the 2 fets in series.

[EEVblog]

The circuit is missing the other side terminal for the current and another FET to separate the 10 K Shunt.

Not needed, the 10k is permanently in parallel, just like on the present design uCurrent.

[neutrino353]

The circuit is missing the other side terminal for the current and another FET to separate the 10 K Shunt. Than the drop on the MOSFET for the 10 mOhms shunt would not be included.
With only one MOSFET the burden voltage including the drop at the FET should be small (e.g. < 100 mV), as there is always the parasitic diode with the FETs.

Could you show me in detail how to do this ? One of the reason I don't use current ranger's circuit and do my own design is that it includes the Fet voltage drop in the 10 mOhm
mode sampling.

I have shown the circuit principle before. The circuit there is a little more complicated with an extra 4 th channel using an TIA and the extra input protection, so that one would not burn the shunts so easy.  Depending on the burden one may get away without the 2 fets in series.

Actually I am using sensing resistors in series in my design but cannot get rid of the FET voltage drop.

Thanks very much that I found your post about your proposed circuit for the current ranger. Your extra FET for the 10K resister solve the "FET voltage drop issue", but require that  the  opamp have very very little bias current so that the current drop across that 10K resistor  can be ignored.
I've do a simulation on Ltspice using FDS6670A mosfet and LTC2050HV opamp  and the result is very satisfactory.

Also , I will add one more shunt stage with ratio 1 : 100 : 10000 : 1000000 to ensure the entire range will have at least 3  digit (0.01 %) accuracy.

There are still to question I don't understand in your proposed circuit :-

1) What is the different of a 4 wire resistance to a normal 2 terminal current sense resistor ?
2) Why using 2 mosfet in series instead of just one when connect the 10mOhm shunt resister to the current source terminal ?

[EEVblog]

1) What is the different of a 4 wire resistance to a normal 2 terminal current sense resistor ?
2) Why using 2 mosfet in series instead of just one when connect the 10mOhm shunt resister to the current source terminal ?

1) It's potentially more accurate. 4 terminal measurement is standard practice in the low ohm world. And the good current shunts down in that range are 4 terminal.

2) Sorry, I did not draw the top + input. They are not in series, they are in parallel. Having the 10R come from the tap of the 0.01R removes the FET voltage drop from the reading.

[prasimix]

4-wire or Kelvin connection can be emulated on the PCB with 2-wire sense resistor (see picture).
I would warmly recommend the ROHM resistors of the GRM100 series (e.g. GMR100HTBFA10L0 for 10 Milioms). So far I have not found anything similar in that price range with TCR of only 20 ppm! It's simply excellent as advertised.