Electronics > Projects, Designs, and Technical Stuff
Current source feedback capacitor
D Straney:
Yeah if you're not looking for a super-fast settling time then might as well get the volume discount and go for approach #1 there. Makes sense with the inputs, the dual-1nF-capacitor on the two inputs threw me off, looked like a differential thing.
Seems like a good way to autorange: the way you phrased that though, I've got to check, are you using the ADC's shunt+ reading for the actual resistance calculation? If you are, then awesome, ignore the rest of this paragraph! If you're not, then you can give a nice bump to your accuracy by not trusting the current source to be perfect: if you do resistance=(measured voltage)/(ideal current), then all the errors of the current source (op-amp offset and drift, input bias*10K, etc.) will show up in your measurement. On the other hand, if you measure the exact voltage coming off the current shunt, then the current source accuracy doesn't really matter as it only has to be somewhere around the right value, and the only remaining errors will be from the shunt resistor(s) themselves and the ADC.
Ooh, nice trick on shutting down the uC's clock during the conversion. Glad you've got the uC digital noise taken care of, but the other possible source of analog noise is from the ADC's own digital section, which will still be doing things during the conversion: especially because while you can reduce uncorrelated white noise by averaging, averaging won't get rid of noise caused by things like spikes on AVDD at certain parts of the conversion process. Probing VDD seems like a good idea, but just for the future I'd at least personally add some extra caps there just as cheap insurance :) May not actually be necessary, but easier than proving that they're not necessary.
I'm surprised the price difference was so small, but hey, if you can spare the extra $0.5 and want to, then go for it! However there is a difference between added resolution and added accuracy. Not trying to be a dick here, just don't want you to have any illusions about suddenly having an 8-digit meter on your hands :) If you've done all the accuracy calculations already then skip this paragraph too, just laying it out in case you haven't yet. Looking at your BOM (thanks for sharing), it's easy to do some sample calculations with the resistors (which seem like exactly the right kind to use for this, by the way):
1A range: 1% initial tolerance, although this can be calibrated out, but what about thermal drift? +/- 10C is a reasonable swing even if you're using this at room temperature, plus maybe another 5C for heating during the pulse (at full load) and 50 ppm/K -> +0.075%, -0.05% range
Other ranges: 0.1% initial tolerance, and as these are 25 ppm/K parts the range due to estimated thermal drift is now about +0.038%, - 0.025%
The ADC's input bias current (+/- 5nA) will create a +/- 0.5mV offset with the 100K source impedance into shunt+ (0.05% of full-scale, 0.5% at the very bottom of the range). Its 10 pA/K drift will create an 0.01% offset worst-case (at the very bottom of the range, again).
Other sources of fixed error are ADC's gain error (+/- 0.01%), and the voltage reference initial tolerance (+/-0.15%). For non-calibrate-able error there's also the ADC's internal reference 110 ppm (0.01%) long-term drift. I'm leaving out the ADC's internal reference drift (because it's tiny near 25C), the ADC's gain error drift, and the ADC's input offset because those end up being way smaller than the other errors.
Overall, it looks like you can get worst-case initial error of +/- 1.2-1.7% (1A range) or 0.26-0.76% (other ranges), and non-constant errors of +/- 0.1% (1A range) or 0.06% (other ranges).
A 47uF tantalum sounds good for the power, and I'd stress again the usefulness of a series diode and small fuse (although by increasing the source impedance of the battery you may also want to bulk up the tantalum's value at that point). Having reverse-polarity protection on all my power inputs has saved me tons of times from my own stupidity, and if you're putting them out into the wild with other people then who knows what they'll do with it. On the subject of protection, it could also be worth putting some 1K series resistors between sense+ and sense- and the ADC inputs; in case of external ESD / somebody sticking a charged cap into it by mistake / etc. it'll at least limit the current through the ADC's input protection diodes a lot and give it a much better chance of surviving. The error added by the bias current through those resistors will be infinitesimal compared to the other errors calculated above.
Also one more thing: some vias at the gnd side of R3 could help - for the 1A range, it'll help spread the high return current to the battery across both the gnd planes, and keep that extra gnd resistance from affecting your measurement as much. Although if you're careful about where the battery- connection is and reserve the bottom gnd plane for signals only (by making the only bottom-to-top gnd plane connection at R3's gnd side), it could also have the effect of making a Kelvin sense for your current shunt to the ADC. I haven't done the numbers and so don't know if the effect is actually significant or not, but if you're aiming for some serious precision, then copper has an absolutely awful temperature coefficient!
Anyways, apologies for the wall of text, this is what happens when I'm waiting for an annoyingly-long test to run at work and need to keep the brain active somehow...
OM222O:
I will add an extra 1uF capacitor to the ADC supply rail and test to see if it reduces the noise or not :-+
I am also taking into account the inaccuracies of the 1.024V reference and don't assume a perfect current source :phew:
I know I will not be getting 400nV accuracy like the datasheet advertises but based on test results from version 2, the 10uV digit was absolutely solid (no jumps / noise) and I went based on that as my accuracy, but the results were much better than that :-/O I think the absolute amount of uncertainty was about +-2uV (almost an order of magnitude better).
Regarding the ADC inputs: the mux is extremely felixable! it can do 4 single channels or 2 differential channels (only between pins 0 & 1 or 2 & 3 or 1 & 2) which is fantastic. It also doesn't make much difference if I take a differential reading or single ended for the load detection: If I take a single ended reading of shunt+ I should compare and see if it's above lets say 1V. If I take a differential reading between shunt+ and 1.024V then I should check to see if it's less than again lets say 24mV ;D
The ADC inputs are all protected via 1k resistors (RN1 & RN2), then they have a 1nF X2Y (feed through) capacitor which suppresses noise to ground and a 100nF capacitor which suppresses differential noise (both are C0G caps and the X2Y is capacitance matched) although I screwed up the resistor network purchase and there is no matching (they are 1% tolerance) but I didn't have issues with differential noise in the few prototypes I have made and I really don't want to re order 250 resistors if they're not causing issues :palm:
For the reverse polarity I actually plan on using a P-Channel fet (DMP3099L-7 ) since I also have a bunch of them ordered from V2 (it was used as soft power but the new LDO already has that option) which means I can re-use the same parts and it also adds battery life since there isn't a 0.7V diode drop. win-win if you ask me :-DMM
The error calculations were very helpful since I didn't bother with them and wanted to do a check after I was happy with the general design (first version was awful! version 2 was better but still had some issues. V3 is almost there but I can still see a few issues with it) so thank you for doing them. it at least confirms I'm on the right track and not totally off! for the resistors I honestly couldn't get anything better unless approaching insane territory (>1$ per resistor) which would obviously blow the budget so I'm happy with these. I would have liked a better 1ohm resistor however they only come in massive packages since I chose a high power rating, >2W to be exact to give some margin, I don't like to run a 1W resistor at 1W, even if it's a pulsed load) and they are less optimized for tempco / absolute tolerance. I can calibrate out the constant errors using a milliohm meter (funny how it's always so much easier if you had one of the things you were making, to help you with making it :-DD) which I don't have. maybe someone can calibrate one unit for me and I'll be able to use that for the rest, but that will have to wait for later.
the grounds will be heavily stitched with vias all around the edges of the board (not present in the pictures I uploaded since they are the last step and I'm still refining the PCB design). the screw holes also use vias (I will enlarge them a bit more) and are connected to ground which will further help with grounding.
I really appreciate the time you put into these posts and it feels nice to have confirmation that I'm not doing things totally wrong from an experienced engineer. Best of luck with the tests and I hope you have more of them ;) that way I will be able to get more valuable information :-+
Jay_Diddy_B:
Hi,
I have had a look at this circuit in LTspice.
First I have to make a model of the Darlington transistor. Since the internal base emitter resistors are unknown, I have to guess the values and measure the current gain until the curve matches.
This is close enough to analyze the full circuit.
I have substituted MOSFETs that are in the supplied LTspice library.
I should get collector of 1mA in this configuration, but the collector current is only 437uA.
The reason is that you need about 0.5mA of base current to turn on the Darlington.
I have attached the LTspice model.
Check this thread for stabilizing a current sink:
https://www.eevblog.com/forum/projects/dynamic-electronic-load-project/
Regards,
Jay_Diddy_B
OM222O:
Thank you Jay_Diddy_B but you had 2 major errors:
1) not all the current comes from V1 :) some of it comes from the base of the darlington pair which is exactly load is placed at emitter, not collector (please read the previous posts)
2) the LT1013 is not even remotely similar to the op amps I was using, i.e: chopper and rail to rail
if you probe at the 1ohm shunt resistor, 1mA is flowing through it:
Also the fets don't seem to be logic level. I don't think this simulation is valid but gives me a good starting point. again thanks for the effort!
Also I'm not sure what V4 does in this case, can you please explain a bit in more details?
Jay_Diddy_B:
Hi,
It was not clear where the load was. (It is case of a picture or schematic is worth a 1000 words).
The current that is regulated is the emitter current of the Darlington transistor.
The op-amp can be replaced by a zero-drift op-amp like the LTC2050. This is a RRIO chopper stabilized part with 3 MHz of GBW.
The op-amp characteristics should not show up in the circuit performance. C1 and R8 set the position of the dominant pole.
It doesn't matter that the Si4412DY have a higher Gate threshold voltage. I am driving them 5V. They should be fully enhanced. I get representative capacitors without having to resort to third party models.
AC analysis
Voltage source V4 is used to measure the control loop gain. You plot V(b)/V(a) to get the Bode plot.
(Try changing R8 or C1)
You can use this to measure the phase margin.
I have attached revised LTspice models.
Regards,
Jay_Diddy_B
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