EEVblog Electronics Community Forum
Electronics => Projects, Designs, and Technical Stuff => Topic started by: TimNJ on April 28, 2021, 03:15:38 pm
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Greetings,
I work in switch-mode power supply design. In PCB layouts done by the company I work for, and many other companies, I have noticed a common practice of notching-out, or cutting copper pours to "force" current to flow over/through certain components, often a parallel bypass capacitor connected to common-return. This is often seen in the EMI filters where copper is purposefully removed as to force current to flow into/over the pad of the component in question. Please see the attached example.
At a very high level, I sort of "get it". The notion of these layouts is that the current may "circumvent" the filter, capacitor, etc. But, beyond that, my grasp on why this approach is useful (?) is limited. I have a feeling it comes down to some sort of transmission line explanation, but not much beyond that.
In my world, low frequency is maybe <10MHz, and high frequency is above that. Is this kind of approach more useful at high frequencies or low frequencies?
Thanks,
Tim
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Well, draw the equivalent circuit, then ask (or check) if that's helpful or not.
Offhand, I would guess on the order of 10nH, and k12 ~ 30%. So, there'll be a zero in the stopband (some allpass effect), where that coupling acts like a tapped choke, but not a classic tapped choke where that zero is a phase reversal, the inductors are in the same direction instead.
I wouldn't expect it matters anyway, as the cap itself is a good ~10nH, and this is all in the range where everything is mushy. Plus coupling from nearby traces, since these things largely lack ground planes (they'd have to be inner planes, given the clearances and ampacities required?), and you've got some switching stuff off to the left there, which is maybe k ~ 1% to the connector or whatever shown here? So, don't expect much over say 40dB attenuation between whatever's in those traces (hmm, snubber diode, so some amperes peak, and lots of dI/dt?) and that.
Tim
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That looks more like 'star grounding' or at least 'star node-ing'
and Ohms law than any sort of "transmission line" to me.
I think your "very high level" interpretation is the right one - you just want to make sure that the lowest impedance path from source to load has no chance of bypassing the low impedance of the capacitor. For a main reservoir capacitor, for instance, you wouldn't want any of the rectifier ripple current being superimposed on the DC output. The same would apply for smaller filter capacitors at higher frequencies.
I don't think you can read any more depth into it than that, other than that is seems good practice.
EDIT: ^ As usual T3sl4co1l has come up with the better / more technical explanation!
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Well, draw the equivalent circuit, then ask (or check) if that's helpful or not.
Offhand, I would guess on the order of 10nH, and k12 ~ 30%. So, there'll be a zero in the stopband (some allpass effect), where that coupling acts like a tapped choke, but not a classic tapped choke where that zero is a phase reversal, the inductors are in the same direction instead.
I wouldn't expect it matters anyway, as the cap itself is a good ~10nH, and this is all in the range where everything is mushy. Plus coupling from nearby traces, since these things largely lack ground planes (they'd have to be inner planes, given the clearances and ampacities required?), and you've got some switching stuff off to the left there, which is maybe k ~ 1% to the connector or whatever shown here? So, don't expect much over say 40dB attenuation between whatever's in those traces (hmm, snubber diode, so some amperes peak, and lots of dI/dt?) and that.
Tim
Thanks. I am trying to understand to what extent this is (likely) old-wives tales design and to what extent it is (likely) useful. I can't say I really understand what you're getting at. True, adding some extra series inductance will change the filter response to some extent. In the image attached, there's already some 100's of uH on either side anyway.
I don't think the designers add these cut-out to intentionally add inductance. And, I do not think you are suggesting as such. But, I think the intended purpose of this layout must be to address a different phenomenon, in which I am trying to understand at a more fundamental level.
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That looks more like 'star grounding' or at least 'star node-ing' and Ohms law than any sort of "transmission line" to me.
I think your "very high level" interpretation is the right one - you just want to make sure that the lowest impedance path from source to load has no chance of bypassing the low impedance of the capacitor. For a main reservoir capacitor, for instance, you wouldn't want any of the rectifier ripple current being superimposed on the DC output. The same would apply for smaller filter capacitors at higher frequencies.
I don't think you can read any more depth into it than that, other than that is seems good practice.
EDIT: ^ As usual T3sl4co1l has come up with the better / more technical explanation!
Thanks. As T3sl4co1l suggested, I think I will try my best to draw the equivalent circuit and what a "non-notched" and "with-notch" schematic might look like. I shall post later. :)
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Here's what I came up with via simulation. See attached image. Does it look reasonable?
For a pi filter consisting of 1uF - 500uH - 1uF...For the "no-notch" condition, assume that the PCB copper area that forms the "T-intersection" of AC source, 1uF, and 500uF is a triangle and that each leg component's lead is in one corner of this copper triangle. Then, model the PCB inductance as a delta connection between the three. I added a few mOhm series resistance to all the components so that the Q wouldn't be so crazy.
For the ideal response (blue), obviously we get a flat roll-off. When there is a continuous copper pour (no notch, black), note a limited high frequency response. Finally, the notched scenario (red) appears to have a steeper roll-off, due to the higher order of the filter compared to the ideal case (due to the modeled parasitic trace inductance)...Not sure how representative that is of reality. The notched scenario does not have the HF response limitation.
Also I acknowledge that using the word "notch" to describe physical PCB layout is probably confusing in the context of filters where that word is also relevant. >:D
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In my opinion doing that is not only useless but detrimental and seems like the type of practice in place in some places where no one has really thought about it, especially from the electromagnetic fields point of view:
1)increases the overall inductance in what should be an overall low inductance wide trace, decreasing filtering effectiveness. Of course for who cares for low frequency switchers
2) In some cases (like the capacitor at the right, with a trace with current flowing on one direction, then at the opposite direction) creates a magnetic slot in the space between them with a field that is double of a simple conductor
3) Again, in close planar conductors with opposing currents the current density is concentrated near the edge of the conductor, so most of the trace width coming and going is useless and lost for HF frequencies. This effect increases inductance for HF even more than if you consider each conductor as a separate entity
I would remove that practice from all PCBs, but given the state of the world, you risk being called heretic and negationist
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Here's what I came up with via simulation. See attached image. Does it look reasonable?
Hm, no coupling between inductors?
The "no notch" case I guess kinda does coupling? There's an equivalent transformer circuit, a delta or wye of inductors -- though the values aren't too physically relevant. That's perhaps closer to the actual "notch" case.
I should just sit down and write it out... the wye version should be most useful, as the left and right leg go in series with the respective branches, while the bottom leg goes in series with the capacitor ESL. So we can simplify that version.
Top right, p.11: http://cc.ee.ntu.edu.tw/~ultrasound/classnotes/ckt2/Chapter8.pdf (http://cc.ee.ntu.edu.tw/~ultrasound/classnotes/ckt2/Chapter8.pdf)
Of course, you need to apply the formula for M as a function of L1, L2 and k.
If k were < 0 (a tapped inductor), M < 0 and you get weird values (as the bottom one goes negative), though this could arguably be helpful if dimensioned just right to null ESL -- again, there's no actual negative inductance here, but it's effectively doing pole-zero cancellation of the capacitor's ESL zero. If (-M) > ESL, then we get phase reversal -- it's having an all-pass filter sort of effect, somewhere up in the stopband.
Whereas for k > 0 (notched trace), it only acts to increase ESL. Meanwhile, the branch inductances drop slightly, but if you're putting much larger inductors there anyway (filter chokes), that's irrelevant.
|M| is only on the order of a few nH.
In contrast, if you use a big blob of copper, you may be increasing ESL directly (your assumption of "10nH between any pair of points" is probably alright here), but the wider conductor may have lower ESL (by on the order of 50%?). So maybe the notched case is 15 or 20nH and the blob is 7 or 10nH. Which means the notched case adds maybe like 3-5nH ESL, while the blob adds 5-7nH, sort of thing. Seems like, well and truly, a wash...
I would say the bigger priority is simply filling in available space. You can't have inductance if there's nowhere for the fields to go. That, and isolating loops by putting distance between them, as there's no ground plane to do anything else against. The latter, isn't something we can always do very much of, in compact PS designs.
So, here's something I did a few years ago, mind it's untested (I haven't had any reason to test this project for EMI yet, it's just a back burner one).
(https://www.eevblog.com/forum/projects/cutting-pcb-copper-pours-to-force-current-to-flow-through-capacitors-etc/?action=dlattach;attach=1215384;image)
For a pi filter consisting of 1uF - 500uH - 1uF...For the "no-notch" condition, assume that the PCB copper area that forms the "T-intersection" of AC source, 1uF, and 500uF is a triangle and that each leg component's lead is in one corner of this copper triangle. Then, model the PCB inductance as a delta connection between the three. I added a few mOhm series resistance to all the components so that the Q wouldn't be so crazy.
Hmm, note that 500uH is pretty uncommon; that would be for explicit DM filtering, while incidental (due to leakage) filtering will be closer to 2-20uH say. This is still much more than 10nH so I don't think this makes any difference to the form of the results -- just making a note of it.
Tim
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Would it be possible to do a comparison on the bench? Maybe take a unit and test it (I guess conducted emissions with a LISN) for a baseline with the cut.
Then take some copper tape and solder it on to make a wide plane and re-test to see what happened.
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Here's what I came up with via simulation. See attached image. Does it look reasonable?
Hm, no coupling between inductors?
The "no notch" case I guess kinda does coupling? There's an equivalent transformer circuit, a delta or wye of inductors -- though the values aren't too physically relevant. That's perhaps closer to the actual "notch" case.
I should just sit down and write it out... the wye version should be most useful, as the left and right leg go in series with the respective branches, while the bottom leg goes in series with the capacitor ESL. So we can simplify that version.
Top right, p.11: http://cc.ee.ntu.edu.tw/~ultrasound/classnotes/ckt2/Chapter8.pdf (http://cc.ee.ntu.edu.tw/~ultrasound/classnotes/ckt2/Chapter8.pdf)
Of course, you need to apply the formula for M as a function of L1, L2 and k.
If k were < 0 (a tapped inductor), M < 0 and you get weird values (as the bottom one goes negative), though this could arguably be helpful if dimensioned just right to null ESL -- again, there's no actual negative inductance here, but it's effectively doing pole-zero cancellation of the capacitor's ESL zero. If (-M) > ESL, then we get phase reversal -- it's having an all-pass filter sort of effect, somewhere up in the stopband.
Whereas for k > 0 (notched trace), it only acts to increase ESL. Meanwhile, the branch inductances drop slightly, but if you're putting much larger inductors there anyway (filter chokes), that's irrelevant.
|M| is only on the order of a few nH.
In contrast, if you use a big blob of copper, you may be increasing ESL directly (your assumption of "10nH between any pair of points" is probably alright here), but the wider conductor may have lower ESL (by on the order of 50%?). So maybe the notched case is 15 or 20nH and the blob is 7 or 10nH. Which means the notched case adds maybe like 3-5nH ESL, while the blob adds 5-7nH, sort of thing. Seems like, well and truly, a wash...
I would say the bigger priority is simply filling in available space. You can't have inductance if there's nowhere for the fields to go. That, and isolating loops by putting distance between them, as there's no ground plane to do anything else against. The latter, isn't something we can always do very much of, in compact PS designs.
So, here's something I did a few years ago, mind it's untested (I haven't had any reason to test this project for EMI yet, it's just a back burner one).
(https://www.eevblog.com/forum/projects/cutting-pcb-copper-pours-to-force-current-to-flow-through-capacitors-etc/?action=dlattach;attach=1215384;image)
For a pi filter consisting of 1uF - 500uH - 1uF...For the "no-notch" condition, assume that the PCB copper area that forms the "T-intersection" of AC source, 1uF, and 500uF is a triangle and that each leg component's lead is in one corner of this copper triangle. Then, model the PCB inductance as a delta connection between the three. I added a few mOhm series resistance to all the components so that the Q wouldn't be so crazy.
Hmm, note that 500uH is pretty uncommon; that would be for explicit DM filtering, while incidental (due to leakage) filtering will be closer to 2-20uH say. This is still much more than 10nH so I don't think this makes any difference to the form of the results -- just making a note of it.
Tim
Mmmm. Interesting. Are you suggesting that it might be useful to model (L8 and L9, for instance) as coupled inductors, 180 degrees out of phase in this instance?
As MasterTech said: "2) In some cases (like the capacitor at the right, with a trace with current flowing on one direction, then at the opposite direction) creates a magnetic slot in the space between them with a field that is double of a simple conductor"
...I've never heard the term magnetic slot, but I think I understand.
Also, regarding notched vs blob approach, I also thought about decreasing the inductance of each delta branch (in the blob case), but was not sure exactly what an approximate correction factor might be, so I left it alone. I was thinking something like 1/3 reduction in inductance.
Indeed in this particular case, I gave the example of an explicit DM filter with large series inductance and large parallel capacitance. The applicability of this filter is maybe 5MHz or less...and based on my crude simulation above, the usefulness of this layout approach may not give any (theoretical) benefit until higher frequencies anyway.
To me, seems like cutting up traces is (generally) not a good idea for high power switching loops where one goal is to keep loop inductance low. In the event of non-ideal ground plane situation, it still may be a good idea to use some sort of quasi-star-ground approach, though. On the other hand, for EMI filters with intentional series inductance, apart from modifying the filter response a little, it may not be hugely problematic to add additional inductance? I understand that sprinkling in some extra nH here and there will probably cause an idealized 3rd order filter to turn into something like 5th or 6th order filter with some peaking here and there.
Thanks.
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Would it be possible to do a comparison on the bench? Maybe take a unit and test it (I guess conducted emissions with a LISN) for a baseline with the cut.
Then take some copper tape and solder it on to make a wide plane and re-test to see what happened.
Indeed, I think I shall give this a try. I feel like it will vary case-to-case, so I don't want to jump to conclusions too soon. My guess is that the usefulness will be limited in terms of DM performance for a typical 100KHz-ish SMPS.
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I've read an app note (from maxim or AD), basically, they say that don't cut the plane, but instead optimized component placement for return path. This is because at freqs above, some MHz return current flows under the trace (provided close proximity to the ground, so 4+ layer boards). So, splitting the ground won't help much, but can make things worse. Although, this article says it might be benefitial to partition the ground plane in some cases: https://www.analog.com/en/analog-dialogue/articles/staying-well-grounded.html (https://www.analog.com/en/analog-dialogue/articles/staying-well-grounded.html) .
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Mmmm. Interesting. Are you suggesting that it might be useful to model (L8 and L9, for instance) as coupled inductors, 180 degrees out of phase in this instance?
No, in-phase. Just add a "K89 L8 L9 0.3" or so to the schematic. Or -0.3 if one is flipped, I don't know. Phasing symmetrical components can be weird...
Anyway, you can try both and see what peaks you get either way. :)
Tapped inductors in these locations tend to have a phase shifting effect (making a non-minimum phase filter), without much effect on the overall response -- and again, with figures like 10nH here and there, we don't expect much effect until quite high frequencies. For example at 50 ohms, that's on the order of 800MHz! Down at 1 ohm it's only 16MHz so YMMV, but it's quite unlikely you'll be able to maintain such low impedances over any meaningful distance.
The real question I think is beside the point:
You can't ask about a conductor in isolation. It's a meaningless question. What is the relation of the conductor to whatever companion conductors are near it?
Since we're not on ground plane, we can't call it a microstrip hairpin network, for example.
The real question then, is not, how should we shape a piece of conductor, but how should we shape the space between conductors?
And note in my example, the space is as narrow as possible (clearance only, with rounded corners to look good, or especially rounded inside corners for better current density).
Also note in my example, I did actually do some concave sections -- basically just to mimic the style, which was not justified at all, and this thread explains why. ;D
Wide conductors also dissipate more heat, increasing ampacity.
You can take it all the way from clearance on same layer, to overlapping on layer pairs. This gives the least possible inductance, and should be seen as the platonic ideal. The shape of the conductors is hardly relevant, but the space between them is key.
The area cropped off to the left, goes to some bypass caps and an inverter, on that board; you may recognize some features here:
(https://www.seventransistorlabs.com/Images/Induction1501.jpg)
That area is done with DC +/- pours for least inductance. The loop inductance at the switching transistors is, hmm, I forget if I characterized that, and if so how much; I do see on the physical board I put some, is it 1R + 10nF?, SMT chip components wired between transistor pins, DC +/-. (The grid of pins, with the grid of screw holes above/below them. Bottom side mounted transistors.) That implies around 10nH loop around the transistors, not bad considering it's a 2-layer board and the top side is taken up with gate connections.
To me, seems like cutting up traces is (generally) not a good idea for high power switching loops where one goal is to keep loop inductance low. In the event of non-ideal ground plane situation, it still may be a good idea to use some sort of quasi-star-ground approach, though. On the other hand, for EMI filters with intentional series inductance, apart from modifying the filter response a little, it may not be hugely problematic to add additional inductance? I understand that sprinkling in some extra nH here and there will probably cause an idealized 3rd order filter to turn into something like 5th or 6th order filter with some peaking here and there.
In any case, these are all at such frequencies well beyond what any regular components are rated for -- you get lumpy responses like this,
(https://www.seventransistorlabs.com/Images/CurveFit1.png)
(https://www.seventransistorlabs.com/Images/CurveFit2.png)
(datasheet in blue, circuit in red)
In the 100s MHz, it even matters simply where the connecting wires run through the CMC, and how the turns stack upon each other; a typical one-layer winding on a split toroid like this component (or nearly like the toroid pictured above; it has a couple turns overlapping, but it's nearly a complete single layer), has the equivalent capacitance between individual turns, and inductance per turn (and mutual inductance between turns), adding up to give many resonances at high frequencies, alternately parallel and series resonant. The parallel resonances are fine (high Z = good filtering), but who knows how low the series resonances go?
In much the same way as you'd simply plop down an RF filter module with standard e.g. 50 ohms port impedances and whatever filter response it has; for power filtering, when you have to deal with such frequencies, you really just want to plop in an already characterized module and not have to worry about component or wiring or layout details.
Or just not generate large amounts of 100MHz+ in the first place, y'know. :)
On a related subject, I did an EMC fix a couple years ago where the power supply was worse than Swiss cheese, no ground plane in sight. (It was a combined PFC + resonant supply, nothing too crazy.) I feel I determined that, at low frequencies (under 10MHz or so), there was a meaningful relationship between component choice/placement/etc.. That is, putting in Y-type caps reduces common mode, X-type or DM chokes reduces differential mode, that sort of thing. But at the higher frequencies, that damn thing is just an uncontrolled mess -- in fact, even just waving an inductive probe several feet away from the bare PCB, it's just a cacophony of noise -- I know you're not supposed to be able to "comb a sphere" but this thing was doing a damn good job trying!*
*Meaning, no matter which way you hold the probe -- the probe is a dipole, sensitive to field direction as well as location [where it's placed]. Well, if the source and probe are both dipoles, of course when they are crossed, you get a null. Well, even for opposite type polarizations (e.g. circular source, linear probe), for any intensity distribution, there has to be some null somewhere around the source. It is said that, you can "comb" the field everywhere but finitely many points -- you always end up with a singularity or null, or pinch or whorl, where all the field lines come together and cancel out.
*Now, it's not like I actually tried exhaustively to plot the field magnitude and direction at all points; most likely it varies by frequency, so I'd find numerous nulls at any given frequency (which satisfies the "no combing" theorem), it's just that because the thing is broadband noisy, I'm always going to find something, in the overall spectrum. So I'm abusing the term a bit here.
*I know, explaining the joke kills it. This is an interesting enough theorem, and probably obscure enough too, that I thought the explanation would be worthwhile.
Once I relaid the design with a ground plane, everything was much more sensible (to the tune of ~ -20dB across the band), and component choice and placement were responsive even out to 60MHz or more, I think.
Tim
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Thanks for your response. I have just read the first line so far..maybe I have some confusion in my head about what is considered in-phase in this case. Currents in each inductance are opposite of each other, so the coupled inductances are out of phase? No?
Anyway, I re-ran the simulation with 0.3 coupling. If I have the phasing right, it's the worst frequency response of all of them. If switch to -0.3, then it's about on par with copper blob.
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I've read an app note (from maxim or AD), basically, they say that don't cut the plane, but instead optimized component placement for return path. This is because at freqs above, some MHz return current flows under the trace (provided close proximity to the ground, so 4+ layer boards). So, splitting the ground won't help much, but can make things worse. Although, this article says it might be benefitial to partition the ground plane in some cases: https://www.analog.com/en/analog-dialogue/articles/staying-well-grounded.html (https://www.analog.com/en/analog-dialogue/articles/staying-well-grounded.html) .
Thanks. Indeed, most EMC experts tend to recommend unbroken ground planes when possible. Though I have almost no experience with high-speed digital design, etc., I feel like this recommendation is often given in that context. For power electronics, still useful to have a ground plane, but sometimes you get bitten if you, for example, dump some big currents into the ground plane and assume that everything's going to be fine.
In my example here, due to some physical constraints, there is often not a ground plane, or at least, not a good one.
I'm still trying to put my finger on the difference between a discussion about ground-planes and what I'm bringing up here. Here, I guess the idea is that the connections between components are not ideal and since this is true, it may be wise to consider how they are being connected together.
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Yes, like that! In phase, you have the peak like the "notch" case (which is I think, the source series-resonant with L8 and C3 -- yes, 10nH and 1uF is 1.59MHz -- essentially an artifact of the source being zero resistance), and either nothing or a trough above that (not sure offhand what resonance that is), the frequency of which will vary with k; then the same asymptote as delta, because both cases add ESL to the capacitor.
Actually I think the delta case is very similar, it's just rather more tightly coupled hence the features are closer together -- notice it ticks up just slightly, before it dives into the trough, and both of these points are rather close together (~2.8MHz, 4MHz). If you adjust the bridging inductor (L3/L5) you'll see a similar change.
So I think the equivalent circuits are doing what I expected -- when the transformer is expanded to a wye (tee) network, the elements just add with nearby inductances, reducing to a simpler L-(L+C)-L ladder network.
Tim
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Thanks for the inputs! You have a good eye (brain, actually) for visualizing resonances. I just plug into LTSPICE with the blinders on. >:D
Tried another experiment comparing K = 0.1 to K = 0.3. If you could theoretically reduce the coupling factor to about 0.1, then seems you might be able to get some high frequency improvement, using this "notch" approach.
So...to reduce the coupling, I guess don't make a trace do a 180 degree U-turn back on itself (like in my original image), and/or...keep larger spacing between these counter-opposed traces? Any ballpark estimates on relationship between spacing and coupling factor?
In this case of this low frequency DM filter, maybe this talk is for naught, but perhaps relevant for higher frequency filters. (FYI, I also made Rs = 0.1 in this simulation.) Interestingly, the delta/blob/no-notch case has better attenuation in the mid-frequency (1-5MHz) band, due to some (lucky?) resonances.
Edit: Hold on, maybe this adding source resistance idea wasn’t such a good one, given how I’m running the simulation. Now all circuits share that series resistance why probably explains why even the “ideal“ case is so cranky looking.
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Corrected simulation to give each circuit it's own 0.1ohm source resistance, not one shared source resistance!
Still basically same comment as above. If the coupling between "notch inductances" is sufficiently low, then it's possible to get some high frequency improvement. Otherwise, performance might be on par with a big ol' copper pour.
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In my world, low frequency is maybe <10MHz, and high frequency is above that. Is this kind of approach more useful at high frequencies or low frequencies?
In my experience with 50-400 kHz DC-DC, if we want to make a good filter then a current has to flow directly through the filter element pins. Oherwise the noise may increase up to several times. I mean this rule works everywere, for the whole frequency range.
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In my world, low frequency is maybe <10MHz, and high frequency is above that. Is this kind of approach more useful at high frequencies or low frequencies?
In my experience with 50-400 kHz DC-DC, if we want to make a good filter then a current has to flow directly through the filter element pins. Oherwise the noise may increase up to several times. I mean this rule works everywere, for the whole frequency range.
That’s interesting. And when you say to “make a good filter”, at what filter frequency range are you talking about? Obviously 50-400KHz base switching frequency, but considering harmonics, I suppose you mean filtering well into the MHz range. Thanks.
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Another aspect may be that by partitioning the current flow between two points, a 'noisy' aspect of the current flow through a particular path can be alleviated which may reduce the noise ingress in to a general gnd grid - such as in the example pcb in post #1 where a noisy signal that uses the RHS terminal pin is being split at the pin pad rather than allowed to flow down the broad trace (to the highlighted capacitor pad) to what appears to be a gnd grid/fill that includes a chassis bolt connection.
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Not being an degreed electrical engineer and at the same time having taken apart a huge amount of gear, I might suggest that the answer is none of the above. Instead consider the possibility that the issues might be mechanical in nature. That is the placement of components may have been impacted by final assembly clearance issues and pick and place issues. That is the designer laying out the board had a bit of a struggle placing everything and probably ran out of time.
The cap on the left seems to be suffering from this. The one on the right is harder to tell as it certainly doesn't make sense to me looking at it visually. However the cap is apparently next to an area for some sort of board connector and a large area kept clear of anything.
There may be a sinister electrical engineering issue at hand to justify the layout or it could be the reality of CAD and dead lines.
As an aside one DC supply failure I dealt with years ago had a problem where the unit failed due to nothing more than a burnt up trace. Similar to what is seen in the picture one terminal went to an I/O pin with a rather fine trace that was pulled form a much heavier trace. The obvious expectation was that little current was expected to flow through that terminal. However with multiple I/O connections to the same bus on the circuit board and no warning as to current capacity differing it is pretty easy to see how too much current was forced through the trace. For me it was an obvious layout problem as the rest of the connections had robust connections to the bus, and most obviously overlooked.
In any event I just wanted to put this out there that maybe it isn't intentional design.
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Not being an degreed electrical engineer and at the same time having taken apart a huge amount of gear, I might suggest that the answer is none of the above. Instead consider the possibility that the issues might be mechanical in nature. That is the placement of components may have been impacted by final assembly clearance issues and pick and place issues. That is the designer laying out the board had a bit of a struggle placing everything and probably ran out of time.
The cap on the left seems to be suffering from this. The one on the right is harder to tell as it certainly doesn't make sense to me looking at it visually. However the cap is apparently next to an area for some sort of board connector and a large area kept clear of anything.
There may be a sinister electrical engineering issue at hand to justify the layout or it could be the reality of CAD and dead lines.
As an aside one DC supply failure I dealt with years ago had a problem where the unit failed due to nothing more than a burnt up trace. Similar to what is seen in the picture one terminal went to an I/O pin with a rather fine trace that was pulled form a much heavier trace. The obvious expectation was that little current was expected to flow through that terminal. However with multiple I/O connections to the same bus on the circuit board and no warning as to current capacity differing it is pretty easy to see how too much current was forced through the trace. For me it was an obvious layout problem as the rest of the connections had robust connections to the bus, and most obviously overlooked.
In any event I just wanted to put this out there that maybe it isn't intentional design.
I'm not quite sure exactly what you're saying, but as I have full access to the board file in the original post, I can clarify some more.
Right side of the board is the IEC AC inlet (C14, C8, etc.). Large clearances to meet the safety standard requirements. The two caps I highlighted are part of a differential mode pi filter. The right most trace, with the most obvious "cut-out" is connected to the primary side common of this power supply.
You are right that the overall layout was driven by mechanical limitations. For a compact power supply like this, the number of (reasonably good) layout possibilities is actually fairly low (talking mostly about top-side THT components.) In this case, the layout engineer must have found that this was (one of) the only reasonable ways of fitting the components he/she needed.
But the copper pour cut-outs are not explicitly "necessary", from any mechanical point-of-view that I can imagine.