Cyclone 4 board - 2 or 4 layers?

[Miti]

This is my first board in Kicad, it is an FPGA board that takes the analog video from HP8590E series spectrum analyzer and converts it to VGA for CRT to LCD conversion. I would like to make this board with JLCPCB so I try to place everything on the top side, as much as possible. I would also like to make it on two layer, if possible, and I would really appreciate your opinion about my layout. Do you think I can get away with this layout or is just a wet dream?
What level of EMI can I expect? I don't intend to do any EMC testing but since it will be installed in a very sensitive instrument, I wonder how that would affect the noise level. The input clock is 27MHz, the maximum internal clock is 336MHz.
The layout is not finalized yet but you'll get the idea.

Cheers,
Miti

[BrianHG]

4 is better, however, here is a successful 2 layer layout for reference, one which draws much more IO and current than yours.  It uses the same Cyclone 4 IC:

https://www.eevblog.com/forum/fpga/fpga-vga-controller-for-8-bit-computer/msg2887522/#msg2887522

The big difference is the decoupling caps are on the bottom except for the PLL decoupling caps and filter ferrite beads.

Separate your linear regulators.  They will get toasty all being in that 1 corner of your PCB.
Since you are using linear, I would place 1 at each corner of your PCB since there is no heat sink.
The 2.5v may be close to the 3.3v as they wont get as hot at the VCC Int 1.8v regulator.

[langwadt]

how much more does 4 layers cost and is it worth the risk and hassle of not doing 4 layers?

[Miti]

The big difference is the decoupling caps are on the bottom except for the PLL decoupling caps and filter ferrite beads.

Separate your linear regulators.  They will get toasty all being in that 1 corner of your PCB.
Since you are using linear, I would place 1 at each corner of your PCB since there is no heat sink.
The 2.5v may be close to the 3.3v as they wont get as hot at the VCC Int 1.8v regulator.

Yes, that’s a big difference for me. If I can get the board fully populated, less the THs, that would be a big plus.

The development board that I have uses the same 3 linear regulators in one corner and they are barely warm. The whole thing takes 140mA from 5v and it has a 7 segment display at full brightness and some LEDs. My first stage is switching from 12V to 5V and then linear to 3.3V, 2.5V and 1.2V but I’m still debating if I should go with 3 switching regulators.

[Miti]

how much more does 4 layers cost and is it worth the risk and hassle of not doing 4 layers?

Ten times more for 10 pcs.

[BrianHG]

The development board that I have uses the same 3 linear regulators in one corner and they are barely warm. The whole thing takes 140mA from 5v and it has a 7 segment display at full brightness and some LEDs. My first stage is switching from 12V to 5V and then linear to 3.3V, 2.5V and 1.2V but I’m still debating if I should go with 3 switching regulators.

That's puny.  Your design is tiny and slow....  Linear is fine.
The PCB I showed has a core running at 125 & 250 MHz, consuming 97% of the fabric which is all running at that full speed + every IO is in use.  The 1.2v linear regulator runs a little too hot to touch while the design consumes over 500ma @ 5v.  However, it functions fine none the less.

[langwadt]

how much more does 4 layers cost and is it worth the risk and hassle of not doing 4 layers?

Ten times more for 10 pcs.

so a few dollars and still a fraction of the component and assembly cost

[Siwastaja]

That spiral power routing you have to resort to with 2-layers is a bit iffy. Even if you bypass it at every power pin, you'll create an interesting LCLCLC loop. I might be worrying for no reason, but I'm saying this because this layout looks very familiar; I made such a board with Cyclone III and gigabit ethernet phy somewhere around 2010 and I never got very far because I had obvious signal integrity issues and then lost interest in the project. I think I used a 240-pin package so it was larger than this and the ETH PHY had similar spiral power routing, but in any case, never again, just in case. Everything will be so much easier with more layers to work with, and proper grounding.

Although, even with 4 layers, you still need to get a bit creative with power distribution given three different voltage buses required.

Look at PCB prices at pcbshopper.com and decide how much worth your time (longer design with fewer layers) and signal integrity (inferior result with fewer layers) are.

[ebclr]

If your video input is composite video take a look on TVP5150 will make your job easier

[Miti]

That's puny.  Your design is tiny and slow....  Linear is fine.

Yes, I know but if I use 3 switching regulators instead of linear, I can use smaller ceramic capacitors and I save real estate. 3.3V is not enough for the input of a 2.5V linear 1117 so I need 12 to 5 switching then three linear. Price wise I don't think there is any difference.

[Miti]

so a few dollars and still a fraction of the component and assembly cost

That's true and if I really need 4 layers, I will not hesitate, I'm just not sure if it is needed in this case, hence the question. I always design with the lowest cost, that doesn't compromise the functionality, in mind, just in case I decide to sell the board.

[Siwastaja]

By all means don't limit yourself to 1117; it's really old and has peculiar output capacitance requirements similar to other parts of the same age. If you look at other possible regulator ICs in parametric search, you are able to find ones with lower drop-out (so that 2.5V from 3.3V becomes possible; current requirement for Vpll is so small that linear reg makes most sense) and may also be stable with smaller output C! Although, they may be more expensive than Chinese 1117 compatibles.

[Siwastaja]

Note that if you are going to sell the thing in any volumes, the PCB cost will be maybe some $2 for 4 layers (compared to maybe $0.50 for 2 layers) so the savings taking the whole BOM into account are meaningless in any design that contains an FPGA, an expensive component.

[Miti]

That spiral power routing you have to resort to with 2-layers is a bit iffy. Even if you bypass it at every power pin, you'll create an interesting LCLCLC loop.

That's my main worry, even though I may be a little paranoid. As Brian said, this is a simple design, power requirements and speed wise.

[Miti]

If your video input is composite video take a look on TVP5150 will make your job easier

It's not that simple, I tried AD722 and the result is not that great. The signals are non standard even if they call them PAL, NTSC, NRM.
Compare the first picture from AD722 with the subsequent from the FPGA.
The FPGA also gives me the flexibility to select different colours for the two intensity levels and some other features.

[Miti]

By all means don't limit yourself to 1117; it's really old and has peculiar output capacitance requirements similar to other parts of the same age. If you look at other possible regulator ICs in parametric search, you are able to find ones with lower drop-out (so that 2.5V from 3.3V becomes possible; current requirement for Vpll is so small that linear reg makes most sense) and may also be stable with smaller output C! Although, they may be more expensive than Chinese 1117 compatibles.

That's exactly what I'm doing now. 

[Siwastaja]

FPGA is never "simple" speed wise. It's not about what clock frequencies you are running at; FPGAs are high-performance devices with high edge rates on I/O. You will be seeing shorter and higher current spikes than with e.g. 8-bit PIC micros and bypassing and power planes matter more. The edge rate matters, even if you switch the output state at 1Hz.

[Miti]

FPGA is never "simple" speed wise. It's not about what clock frequencies you are running at; FPGAs are high-performance devices with high edge rates on I/O. You will be seeing shorter and higher current spikes than with e.g. 8-bit PIC micros and bypassing and power planes matter more. The edge rate matters, even if you switch the output state at 1Hz.

Ok, I will move to 4 layers:

Top   Signals + decoupling + GND plane
L1     GND plane
L2     Power + GND plane
Bot    Not many signals left + GND plane
Lots of stitching vias.

Does this sound reasonable?

[BrianHG]

FPGA is never "simple" speed wise. It's not about what clock frequencies you are running at; FPGAs are high-performance devices with high edge rates on I/O. You will be seeing shorter and higher current spikes than with e.g. 8-bit PIC micros and bypassing and power planes matter more. The edge rate matters, even if you switch the output state at 1Hz.

Ok, I will move to 4 layers:

Top   Signals + decoupling + GND plane
L1     GND plane
L2     Power + GND plane
Bot    Not many signals left + GND plane
Lots of stitching vias.

Does this sound reasonable?

When you have a dedicated solid GND plane, do not make the mistake of painting a flooded GND on top and bottom as being a good thing.  No signal in your circuit exceeds 27MHz.  This is not a microwave design.  I would only flood a little fill under the FPGA to the GND heat sink pad.

[BrianHG]

Switchers may generate EMI which your all linear measurement instrument may not be designed to filter out.
Not to mention the generated EMI on the FPGA VCCIO power rail which you are using as a 2 bit ADC.

You do not need big caps for linear regulators.  10uf will do.
Ceramic ones will work, but because of capacitance loss VS input DC voltage, just use 10uf 16v XR7 size 1206 or 1210.  At the voltage you are working at, you will get the full 10uf.

See example 4.7uf chart below:

[ejeffrey]

FPGA is never "simple" speed wise. It's not about what clock frequencies you are running at; FPGAs are high-performance devices with high edge rates on I/O. You will be seeing shorter and higher current spikes than with e.g. 8-bit PIC micros and bypassing and power planes matter more. The edge rate matters, even if you switch the output state at 1Hz.

Ok, I will move to 4 layers:

Top: Signals + decoupling + GND plane
L1     GND plane
L2     Power + GND plane
Bot    Not many signals left + GND plane
Lots of stitching vias.

Does this sound reasonable?

That's overkill for this application

Top: high speed signals + decoupling capacitors
L1: GND
L2: power (split if needed)
Bottom: low speed signals + low power polygons if needed

You put the high speed signals on top so they don't have to route through vias. Low speed signals go on the bottom if needed.  A single ground plane needs no via stitching.

Yes you can flood all the unused area on the outer layers with ground flood at the end but it doesn't really do anything in most circuits.

[Miti]

When you have a dedicated solid GND plane, do not make the mistake of painting a flooded GND on top and bottom as being a good thing.  No signal in your circuit exceeds 27MHz.  This is not a microwave design.  I would only flood a little fill under the FPGA to the GND heat sink pad.

Yes you can flood all the unused area on the outer layers with ground flood at the end but it doesn't really do anything in most circuits.

It's good I asked, I would have done exactly that. Thanks Brian and ejeffrey! One single solid ground plane it is.

[Siwastaja]

No signal in your circuit exceeds 27MHz.

Total bullshit. You are guaranteed to exceed some 100-200MHz easily, even if you set all the drive strength settings properly and add series termination resistors to all signals.

Likely you'll have some serious components at 1GHz.

FPGA IO is fast. Repetition rate is meaningless, actual frequency components matter and that is defined by edge rate alone, and that is defined by the types of driver components you use (i.e., FPGA), not the application even if it's not using the full performance capability of the FPGA.

[BrianHG]

No signal in your circuit exceeds 27MHz.

Total bullshit. You are guaranteed to exceed some 100-200MHz easily, even if you set all the drive strength settings properly and add series termination resistors to all signals.

Likely you'll have some serious components at 1GHz.

FPGA IO is fast. Repetition rate is meaningless, actual frequency components matter and that is defined by edge rate alone, and that is defined by the types of driver components you use (i.e., FPGA), not the application even if it's not using the full performance capability of the FPGA.

How is it you could not recognize that I was talking about the digital signal integrity in Miti's circuit and not about the turning effects of an RF amplifier's impedance or balanced multi-GHz serdes signals?

[Miti]

What do you know about Torex Semiconductor? I'm looking at these two regulators:

https://www.digikey.ca/en/products/detail/torex-semiconductor-ltd/XC6210B252MR-G/2138117
https://www.digikey.ca/en/products/detail/torex-semiconductor-ltd/XC6222B121MR-G/2138183

[BrianHG]

What do you know about Torex Semiconductor? I'm looking at these two regulators:

https://www.digikey.ca/en/products/detail/torex-semiconductor-ltd/XC6210B252MR-G/2138117
https://www.digikey.ca/en/products/detail/torex-semiconductor-ltd/XC6222B121MR-G/2138183

Their heatsink on their package can only dissipate a puny 250mw.  Do your current and voltage drop calculations to make sure they wont overheat.  Compare that to the the LM1117 you are currently using.

[Miti]

That's 312mA on 2.5V and 119mA on 1.2V from 3.3V. PCB mounted with a bit of copper around, I expect them to dissipate at least 350 - 400 mW.
Anyway, it may be a bit marginal since I don't know how the current is distributed between the voltage rails. Yeah, I know that Intel has a power estimator ...

[BrianHG]

Play it safe....  You are placing this PCB inside another device.  You want clearance for heat coming from that device as well.

Also, the 2.5v should have very little current.  The 1.8v core probably has the higher current.  And, since 1.8v is further from your 5v source, it will generate more heat.

Also, if you look at TI's data sheet for the LM1117, it has copper GND layout recommendations for the GND heatsink pad with which levels of thermal conductivity you will receive.

[langwadt]

Play it safe....  You are placing this PCB inside another device.  You want clearance for heat coming from that device as well.

Also, the 2.5v should have very little current.  The 1.8v core probably has the higher current.  And, since 1.8v is further from your 5v source, it will generate more heat.

Also, if you look at TI's data sheet for the LM1117, it has copper GND layout recommendations for the GND heatsink pad with which levels of thermal conductivity you will receive.

the LM1117 has Vout on the tap and is picky about what output cap you put on it

[Siwastaja]

Consider doing Vcore=1.2V with a switcher from 5V. My secret go-to sauce: SC189CSKTRT and MAMK2520T2R2M + 0603 or 0805 MLCCs, because I don't like generating heat. Not much more expensive or bigger than a linear solution.

Vpll = 2.5V should be very low current and good for linear reg from 5V or from 3V3, but do verify this from the datasheet.

[Miti]

Yes, I think this is the best solution, I was contemplating it. Have you tried that inductor? Looks like the DC resistance is a bit higher than recommended in the IC data sheet.

[Siwastaja]

Yes, I think this is the best solution, I was contemplating it. Have you tried that inductor? Looks like the DC resistance is a bit higher than recommended in the IC data sheet.

Yes but not at full output current but some 500mA so heating is negligible. Of course, do your own loss calculation.