Signed BCD numbers for ALU design

[owl_uk]

The use of some numbers as negative values applies to the number as a whole, not to each individual digit.  So, if we take a four-digit number as an example, we have the (unsigned) values 0000 - 9999, which if we're using ten's-complement can be used to represent the range -5000 - 4999.  Values between 0000 and 4999 simply mean their normal positive value, and those between 5000 and 9999 represent the negative numbers -5000 to -1 respectively.  It's only the most-significant digit that can't be greater than 4 before the number as a whole becomes negative.

Oh I get it now.  So if we stick to 4 digits for simplicity, you get 9999 for -1, 9998 for -2, etc.  And you can use your normal adders/subtractors.  And if it starts with a 9 it's negative, otherwise it isn't.  You still then need some logic if you want to display the number correctly, though, right?  You can't just connect the bits to a 7 seg decoder like you can with an unsigned BCD number.   Also it isn't a simple matter of mapping digits, because 9999 becomes -0001.  So 9 maps to '0' for the first 3 digits and '1' for the last.  Is there an easy trick to fix this?

[Abstr7ct]

I think that it somewhat clicks with me now. I don't want to go into more details about how I understand signed BCD using 10's complement, nor how the whole arithmetic circuit would be designed, but I've the idea that the circuit would need some conversion logic. Say that the user has the opportunity to enter a signed BCD digit (composed of 4 bits) from 0-9, signed or unsigned, then the output must be converted into 8 bits. For example, if the user inputs -6, then the converter must output 94 (1001 0100). Is this correct?

[Abstr7ct]

Say that the user would like to perform the operation (-9-9). The circuit should allow him to input 1001 for number1 and 1001 for number2. It will take 1001 and perform 4 bits-to-8 bits conversion logic inside for each number. 1001 0001 (the 10's complement of 09 which is -9) will be one input of a 2X quad 2-to-1 multiplexer. The second input is the normal positive number expanded into 8 bits (0000 1001 = 09). The control line of the Mux will determine if the 8-bits output would be the normal number (0000 1001) or the 10's complement (1001 0001), and this decision goes back to the user.

Let me do the operation in binary:

 1001 0001
 +
 1001 0001
----------------------
1 ---> carry out (don't care about it in the design, but may be useful to indicate a negative value for decoding/display purposes)
  0010 0010
  0110 ---------> this is for BCD correction (add 6)
  ------
  1000 0010 = 82 --> This would be the negative (10's complement) representation of 18.

The sum will have a double number of bits compared to the input coming from the user. A 64-bit input of 16 BCD digits will have a 128-bit output (16×8) since each BCD digit will be represented by 8 bits inside.

How is that design flow?