Electronics > Projects, Designs, and Technical Stuff
DC load using a CPU cooler
Kevin.D:
--- Quote from: timb on September 22, 2014, 01:16:03 am ---@Kevin.D These MOSFETs are specifically designed for linear operation in the SOA, so the graphs in the datasheet are pretty accurate for the conditions we’ll be using them in.
--- End quote ---
No it isn't, the conditons you will be using them aren't the same conditions that those soa graphs are plotted .
IF you look at the data sheet you see those conditons that the sao are taken in is at a fixed case temp .(you will see T.C =25 ,or t.c =75 or something) .
For a normal use you can't hold the case at some fixed temp unless your using a nice cryogenic cooling fluid like they do when they do these soa plots .
You have to transfer heat from a transistor to a heatsink via a tab .which has an extra
thermal impedance Rth c-s (case to sink thermal resistance ,also any extra thermal resisitance of sil pad's if you use them) .
IF you'd had looked at the soa plots on the graphs and noted the various power's being dissipated at the junction temp of 150 then you would have noticed this
value (150 - case temp) = Rth j-c * power dissipated ( i.e these soa at dc only plot rth j-c * power .they dont include any other thermal resistance).
Being able to use your Rth's to calculate junction temp @ a certain power dissipation (because junction temp is the one that really matters )is really simple to do . And if you can't do that first basic bit then you aren't yet ready to design a multiple mosfet electronic load.
Regards
timb:
Actually, IXYS has graphs for Tj @ 25, 75 and 150c...
Anyway, I'm not sure what your point is? Obviously you need to know the Tj at a certain power dissipation. Calculating it is (as you pointed out) simple.
My point is that IXYS also provides graphs for a range of junction temps for these MOSFETs, as they're designed to run in the SOA.
Sent from my Smartphone
mrflibble:
--- Quote from: microbug on September 22, 2014, 06:57:24 am ---I wonder if thermal graphite is conductive, because if not, it could insulate the drains of the FETs.
--- End quote ---
By itself PGS is a good electrical conductor, but Panasonic also manufactures sheets with an insulating film.
microbug:
What should I do for reverse input protection? The max sink current is 20A - I'm planning to have a high-current diode in a TO-247 package on the heatsink pad (heads up @timb!).
Also, what about the binding posts? I could use 4mm banana jacks which are often rated for 20A, but what about those hex-screw ones on the BK precision loads - would they offer a significant advantage?
I'm currently redesigning the power stage.
EDIT: the DAC I'm using is the DAC8411 from TI. I read that most DACs have buffered output stages, and so can't get lower than 10 or so mV to ground. Is the right approach to add, say 20mV negative offset in hardware and to trim in software (the negative supply voltage for the op-amps is -2V)?
timb:
By the by, made this up quickly in Pixelmator:
The dimensions are loose, based on an image from Arctic’s site that showed the width and height at both angles.
@microbug Using a positive offset is easier sometimes. TI even makes dual output voltage references now that have Vref and Vref/2 outputs; specifically designed for single supply bi-polar applications. For your application you’d use it like this: Say you want a 0 to 2.048 output range. Get a TI REF2040 and use the 4.096 (Vref) output as the reference for your DAC; then use the 2.048 (Vref/2) output to bias your OpAmp.
Now your control range will be 2.048V to 4.096V which is the same as 0V to 2.048V! The other benefit is it will reduce overall noise between the DAC and OpAmp since they’re being powered from the same source.
Anyway, it’s just one approach, but one that I like. =)
Navigation
[0] Message Index
[#] Next page
[*] Previous page
Go to full version