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Electronics => Projects, Designs, and Technical Stuff => Topic started by: blueskull on April 25, 2016, 12:17:18 pm

Title: DC UPS design for critique
Post by: blueskull on April 25, 2016, 12:17:18 pm
Attached is my DC (unregulated 12~24V, actually 4*lipo voltage output) UPS for Intel NUC (SNB to Broadwell, not compatible with the new quad core Skylake one).
This UPS charges form USB, then when input is down, it enables the output, powering the NUC from its quad lipo battery.
The batteries are rated 25C 250mAh each, that allows up to 6.25A discharge, more than enough for the 30W mini PC.

The charger implements charge pump method, this is a cheap way to do constant current charge of multiple batteries in series.
Since I can individually control the charging process, I do not need balancing circuitry anymore.

The entire thing is controlled by a 8-bit MCU, EFM8UB10G16G, this chip comes with integrated 5V->3.3V LDO and USB functionality as well as USB VCP library.
It also comes with 3 channel PWM, here I used 2 of them configured in complementary mode, to form an interleaved charge pump.

ADC input selection is done with a CD4051B. I did not use multiple resistive ladders and multiple MCU ADC channels, to preserve battery life caused by resistive ladder current.
The NPN transistors near CD4051B are for logic level translation since CD4051B is a CMOS device, not LVTTL device.

The 74AHCT08 serves as both logic level translator and or gate to control individual single battery charging process.
The 74LV245A is used as MOSFET gate driver for charge pump MOSFET pairs (BSD235C).

This entire thing including 4 batteries will be fit in the space of a 2.5'' HDD, so I can integrate the UPS inside the NUC. Its output is directly parallelled to NUC's power input.
Here I assume the power source of NUC can only fail open, not fail short (which makes sense since the only reason it fails is because a mains blackout).

The price is quite high for a DC UPS without regulation, but seems like I can not squeeze out even a single red cent.
The prices in the BOM are unit price at one build's quantity from Mouser, all part numbers are Mouser part numbers, the BOM does not include batteries.

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Known issues:
1. The only thing prevents the battery from being overcharged is the output diode, if it fails, a fire is inevitable.
2. I designed a diode leakage bleeding circuitry, but it can not handle a dead short output diode situation.
3. This entire design relies on USB power to operate, so it can not cold start a computer. This is intended.
Title: Re: DC UPS design for critique
Post by: Paul Price on April 26, 2016, 04:28:34 pm
Creating an elegant design for your UPS is costly, a simpler approach to accomplishing your goal is very likely.
Buying parts from Mouser is the very highest cost way of filling your BOM. You should  consider alternatives such as Ebay or Allibaba to get good quality parts at a reasonable quantity, and probably at 1/10 the price you shell out to Mouser.
Title: Re: DC UPS design for critique
Post by: Apollyon25_ on April 28, 2016, 03:42:23 am
You wanted a critique, so...

I find your schematic incredibly difficult to read.

You have a huge net label legend taking up a third of your sheet and a massive title taking up another 1/4.

Then you have a large amount of redundancy in your design which can be abstracted out to a second sheet, though once you clear out some space this likely isn't needed.

(I'm guessing Altium because it looks like Altium...)
You've used netlabels, which is great, but there are also power ports which you've not used at all for the power and ground rails. Which would de-clutter a bunch of those parallel wires. Also these are handled differently by the compiler depending on project settings.

I should also state I personally HATE floating net-labels. i.e. lets play where is the other end?? Lazy schematic editing...

The interconnects between the micro and your mux/gate go left to right, right to left, up to down, down to up... so much confusion! Put a standard AND symbol in the library part for U3 or put some text with it "In A/B, Out Y, AND" or better yet split the library part into gate 1, gate 2, gate 3, gate 4, and the power pins separately, so you can rearrange to make it more readable. This makes checking you have adequate decoupling easier also.

Put pin numbers on the library parts and values of parts on the schematic. This will make debugging actual hardware easier.

Redraw this so input is on the left, output is on the right, most positive voltage is at the top, GND (or negative) at the bottom. i.e. standard drawing conventions.

My very early attempts at schematics were extensively red-penned until I learnt how to draw a schematic neatly that let readers see what it did, without having to play "what is that wire?", "where does that net label also go?", "what was I looking for again?" think of this as paying it forward.

 
Title: Re: DC UPS design for critique
Post by: Apollyon25_ on April 28, 2016, 09:16:30 pm
In earlier versions of AD, net-labels could only be used entering a bus, though they removed this requirement pretty quickly. Though the one use I have for them is for pin swapping during routing - I was put off the pin-swapping tool when it first came out because it was buggy, haven't used it since. See pin swap example.

Power ports are functionally net-labels, but using standard drawing conventions.
See small example of net labels vs power ports.

As long as the net-label assigned to the power port is consistent they'll be connected.
I use "+3V3_A" or "+2V048_REF" etc for supplies (bar symbol) and the small arrow for GND, the chassis symbol for equipment GND, and the parallel bar arrow symbol for EARTH - then these get specific net names GND or CHASSIS or EARTH.

Its pretty easy.

AD will then allow a ports and netlabels global, or local or combo of both setting in the compiler to restrict their respective scope of application.

I've been trying to think of an occasion where the pin numbers were omitted from the symbol in the schematic, and I have you say, you're the first. I've been doing electronics for 30 odd years.
The first time you go to debug this, will be the time you realise why everyone puts pin numbers on the schematic. The second time you go to debug it, will be the time you edit the schematic to put all the pin numbers in.

Be interested to see your revised schematic.
 ;D