| Electronics > Projects, Designs, and Technical Stuff |
| DCF77 PM receiver (radio clock) |
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| capt bullshot:
--- Quote from: ogden on April 10, 2019, 08:52:33 am --- --- Quote from: capt bullshot on April 09, 2019, 09:55:06 am ---A 20 year old real DSP is still more capable than this class of uC in terms of signal processing. --- End quote --- Sure. Yet it is still quite good for 16bit fixed point DSP tasks (link to M4 DSP presentation as pdf). It has saturated integer math, 2-way 16bit SIMD instructions that includes single cycle multiply-add. 16-bit complex 1024-FFT in <=100k cycles IMHO is pretty impressive for MCU you can get for 2$ (stm32f301). --- End quote --- Yes, I've seen impressive stuff done on the STM32F7 discovery board, and I've done digital control loop stuff on a STM32F3 myself, I was quite impressed of how fast I could run the ADC sampling and control loop written in C (not assembler) and using floating point arithmetic. In fact, the same control loop executed somewhat faster using the FPU than the "good old fashioned" fixed point integer stuff. But what I miss with these Cortex-M cores is the ease and effectivity of e.g. the ADSP-21xx architecture assembly language. This lets you do your typical FIR filter at 1 cycle per coefficient plus 4 cycles overhead. Cortex-M7 with its dual issue pipeline can't do this yet and is more complex. --- Quote --- --- Quote from: capt bullshot on April 09, 2019, 11:03:49 am ---This project "just happened" bit by bit and step by step, without having a polished concept of how to do it at the very beginning. --- End quote --- There's always option to reconsider. I find your project unnecessary overengineered and would have bitter taste finishing such because less is more for me. If I were you, I would take stm32f301 and make better version of mentioned receiver. In addition to M4 core and fast ADC, f301 have programmable gain opamp needed for this app. BTW that project can be improved as well - by replacing lowpass filter with narrow 78-KHz tuned bandpass. --- End quote --- The available F3 series nucleo boards were too small in terms of on-chip RAM for this project, so my choice was the L432. The signal processing (receiver) part can be done with less memory than I used now, anyway, I needed larger buffers for the decoder part. My rough estimates showed 8K RAM (that is available on the F3 nucleo module) were way too small. I'll finish this one the way it is, evaluate how it performs regarding the short and long term stability of the 10MHz and PPS outputs, and at some point I might start the next one based on that experience. |
| dietert1:
Here is a link with a description of a digital DCF receiver i made using a HP E1430A VXI module. Written in German but you can probably use an automatic translator. http://www.cadt.de/dieter/dcf/Praezisionsfrequenzmessungen.pdf Also i agree that the Cortex M4 is strong in comparison to many traditional DSPs, since you can do everything in 32 bit. And if you have an optimizing compiler like IAR, at clock frequencies like 100 MHz it can be used even for high end audio. Regards, Dieter |
| ogden:
--- Quote from: capt bullshot on April 10, 2019, 10:14:29 am ---The available F3 series nucleo boards were too small in terms of on-chip RAM for this project, so my choice was the L432. --- End quote --- Your approach could need plenty of memory. dsPIC of mentioned project has 2KB RAM ;) It is wise to use "overkill" chip for prototype rather than late into the project realize that MCU of choice is too small/weak and you have to start it all over again on another chip or even worse - different MCU architecture. Thou you need discipline while using "overkill" chips. Some programmers tend to cut corners writing memory and performance-inefficient code in result. Most of the PC soft bloatware are fine example for that. BTW using single ADC, thus interleaving I/Q samples kind of destroys whole idea of "no compromises" zero-IF design. For IQ sampling you definitely need two synchronous ADC peripherals. |
| Kleinstein:
--- Quote from: ogden on April 10, 2019, 12:09:23 pm ---..... BTW using single ADC, thus interleaving I/Q samples kind of destroys whole idea of "no compromises" zero-IF design. For IQ sampling you definitely need two synchronous ADC peripherals. --- End quote --- There is nothing good in using a zero ZF IQ sampling in hardware. It causes several HW problems, especially coupling back to the antenna and also DC drift of the ADCs / corresponding amplifiers. Zero ZF is a good thing in the virtual / software word. If really needed one could still use an interleaved ADC for I/Q sampling: just add a suitable delay circuite/filter. At zero ZF and thus a quasi DC a delay does not cause a significant phase shift :-DD. At least the early conversion stages (go from 1. ZF to Zero ZF IQ data, carries PLL, maybe even the PLL for the sync of the PM part) can be done in real time as the data come in. So no need to save much data. |
| ogden:
--- Quote from: Kleinstein on April 10, 2019, 12:24:05 pm ---Zero ZF is a good thing in the virtual / software word. --- End quote --- Right. Also it is good for cost-sensitive "pure silicon radio" ASICs. IQ sampling shall not be used *especially* when hardware is capable of best possible radio architecture - direct RF sampling. You sample filtered by narrowband (preselector) filter 1KHz wide DCF77 "channel" at 70KSPS (3rd Nyquist zone undersampling) to get 7.5KHz digital IF, then convert to IQ baseband digitally using precomputed sin/cos table. [edit] Those sampling & IF frequencies are just example. One may consider another values that are perhaps more suitable for intended purpose |
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