Electronics > Projects, Designs, and Technical Stuff
DCF77 PM receiver (radio clock)
(1/4) > >>
capt bullshot:
Recently, I've started a new project, building an DCF77 (German / European radio clock) receiver in PM (phase modulation) mode.
The common commercially available radio clocks (for DCF77 usage) all use the simpler AM mode, but PM mode can provide better accuracy and higher noise tolerance.

It's still work in progress, but I've got a working prototype:
http://wunderkis.de/dcf-rcvr/index.html


Kleinstein:
I don't think it is a good idea to have the ZF to be digitized by the µC at zero. It starts with the odd divider and possible coupling from the clock to the antenna. I would more consider running the I/Q mixers (probably Tayloe -mixer) with something like 70 KHz and this a ZF of 7.5 kHz.
Going to a real super-het receiver with a non zero ZF helps avoiding coupling back to the antenna, as some of the gain can be behind the mixers.

One may not even need I/Q mixers anymore if there is a sufficient filtering, but they could help avoiding mirrored bands.

So there would be a little more math in the µC, but easier hardware. If the clock (more like an VCXO) is also driving the µC, the now CPLD block may be just a 74HC74, if needed at all.
capt bullshot:

--- Quote from: Kleinstein on April 09, 2019, 09:36:07 am ---I don't think it is a good idea to have the ZF to be digitized by the µC at zero. It starts with the odd divider and possible coupling from the clock to the antenna. I would more consider running the I/Q mixers (probably Tayloe -mixer) with something like 70 KHz and this a ZF of 7.5 kHz.
Going to a real super-het receiver with a non zero ZF helps avoiding coupling back to the antenna, as some of the gain can be behind the mixers.

--- End quote ---
You're right, LO coupling is one of the reasons I needed the ADC offset auto zero. Anyway, these Cortex-M4 aren't quite real digital signal processors, by mixing to DC I can get away with
quick and dirty (or just lazy) signal processing in C at a moderate sample rate (3875Hz).


--- Quote ---One may not even need I/Q mixers anymore if there is a sufficient filtering, but they could help avoiding mirrored bands.

So there would be a little more math in the µC, but easier hardware. If the clock (more like an VCXO) is also driving the µC, the now CPLD block may be just a 74HC74, if needed at all.

--- End quote ---

No doubt, this can be done by directly sampling the carrier (no LO and mixers at all), but most probably not using that particular Cortex-M4. A 20 year old real DSP  is still more capable than
this class of uC in terms of signal processing.

NivagSwerdna:
You might find this an interesting read too... http://www.marvellconsultants.co.uk/DCF/

I'm thinking about giving up on DCF (and MSF) since interference with local sources is making it problematic for me to receive them.
Kleinstein:
I don'T know the M4, but the processing needs for the rather low, maybe a 10 kHz ZF are not that high.
A M3 ARM should be well fast enough. I even though about using a similar scheme with an AVR  (using some 2.5 kHz ZF) - though in this case it could get close with the speed.

The extra processing needs for a non zero ZF are not really high:
1) Step the virtual ZF phase by an addition and cut away the highest bits
2) get sine and cosine values from a table
3) 2 multiplications (16 bit integers) for each ADC channel and 4 additions/subtractions to combine the 4 signals
This should not need much more than about 1% of the processor speed if the sampling rate is not very high.

Mixing to zero ZF is a little easier for software, but can be a real nightmare with coupling / shielding.

By not needing I/Q I meant still keeping a mixer, but only a simple 1 phase mixer. The  phase info is still there from the IQ step done numerically.
Navigation
Message Index
Next page
There was an error while thanking
Thanking...

Go to full version
Powered by SMFPacks Advanced Attachments Uploader Mod