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| DDR2 chip how slow can you go? |
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| bson:
--- Quote from: JohanHoltby on August 30, 2019, 03:09:42 pm ---And by using the FMC I will get a lot of less headache. --- End quote --- Just be aware that many STM32 packages have an abbreviated FMC interface. Especially the smaller packages either omit it altogether or have only a small subset of signals to drive things like 8080-bus interface LCD controllers (where data matters and only a few address lines are provided in case you need them for arbitration and addressing logic). On chips like the F103 I've found you will need the full density BGA packages to get the full FMC, and even then it's often pin sharing with other precious functions, and you might find yourself unable to use it at all with any amount of pin or port swapping. |
| Yansi:
FMC is not FSMC peripheral and secondly he may be more concerned he probably can't do the layout for the multiple chip high capacity SDRAM bank alltogether. (Even though such layout may not be difficult at all, but judging from the style of questions and lack of basic understanding, there may be quite steep learning curve to be aware of) Note: interfacing a huge SDRAM bank is never considered doable with any small package. Likely 176pin one required. |
| daqq:
--- Quote ---Great name on the project will stick to it :). Yes its that one. I have been looking in to FPGAs as an alternative but the great challenge is that I need 80 analog in at about 1Msps per board at low cost and the I would need external ADC or more costly FPGAs with ADC built in to it. Pleas if you got any suggestions for FPGAs I'm all open. --- End quote --- Unless you need isolation, then at 80 channels per board you're likely better off with one hefty FPGA and 10x simultaneously sampling 8 channel ADCs ( such as this: http://www.ti.com/product/ADS8598H# or https://www.analog.com/en/ltc2320-12 ). The price per chip is fairly large (though cheaper ones exist), but at a quick guess it might be cheaper than an MCU + Hacked RAM. Essentially per channel, let's say you manage to hack a cheap (3USD) DDR2 memory to play along with a cheapish STM32 (say, 2-3 USD), then you get 6 USD per channel. With a single 10 USD ADC such as the https://www.analog.com/en/products/ltc2320-12.html#product-overview you get 0.95 USD per channel. The processing stuff (FPGA) will be more expensive, but will be single and the costs for this will be divided between all of the channels. |
| Yansi:
Why do you even consider hacking the ram? Considering this is basicaly likely not doable at all, otherwise don't you have anyhing better to do than hacking what is way easier done the proper way? I am even lacking any explanation what he will do with all hose data in the memory or any further explanation of the project. |
| nctnico:
--- Quote from: JohanHoltby on August 30, 2019, 03:09:42 pm ---Wow such much great thoughts Thank you all! So what I can conclude is that I should not do the DDR2 since it has speed requirements due to ?????. The refresh time is required to be 64ms. The alternative would be to use SDRAM since that is not requiring a curtain speed. And by using the FMC I will get a lot of less headache. I will be generating about 1 mega sampels per second from up to 16 channels. So 16 mega byte per second of data in worst case scenario and about 5-10 seconds of data. When i did some calculations I noticed that FLASHs will not be an option since this will be running 24/7 365 days per year. The requirements is not a hard requirement and I have a lot of workarounds that might work, like only storing the value furthest away from the previous value during a 8 sample cycle or similar. The end product is a production test tool so strange spikes and such is of great interest. --- Quote from: daqq on August 29, 2019, 09:26:02 pm ---How about using a small FPGA? If this is for your all-seeing-scope project ( Here ) then things might actually get simpler (and comparably priced) with the proper FPGA. --- End quote --- Great name on the project will stick to it :). Yes its that one. I have been looking in to FPGAs as an alternative but the great challenge is that I need 80 analog in at about 1Msps per board at low cost and the I would need external ADC or more costly FPGAs with ADC built in to it. Pleas if you got any suggestions for FPGAs I'm all open. --- End quote --- I have the feeling that by the time you have designed this you spend more money compared to just buying a data acquisition system. Unless ofcourse this has to become a product. But even then this is likely for a niche market. I'd optimise the design for the least amount of R&D effort and risks. Starting with low cost parts is not the good direction because it will lead to a large amount of effort to make it work. IOW: use a cheap FPGA (Xilinx Spartan series for example) to read a bunch of ADCs and stream the data into a PC using PCIexpress. Inside the PC you'll have easy access to (fast) data storage and analysis. |
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