Author Topic: DDR2 chip how slow can you go?  (Read 5931 times)

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Offline Yansi

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Re: DDR2 chip how slow can you go?
« Reply #25 on: August 30, 2019, 07:17:01 pm »
Yeah and then spend the next two years developing a kernel driver for the pciex card. ^-^
 
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Offline nctnico

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Re: DDR2 chip how slow can you go?
« Reply #26 on: August 30, 2019, 07:20:57 pm »
Yeah and then spend the next two years developing a kernel driver for the pciex card. ^-^
Just hire someone who can.
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Offline bson

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Re: DDR2 chip how slow can you go?
« Reply #27 on: August 30, 2019, 07:39:23 pm »
I would second the idea of an SD card slot and an SDIO bus interface.  16MB/s should be straightforward.  Use FAT32 and have a PC program pre-format the cards to have a single big continuously allocated data file that you use as a buffer.
 

Offline Yansi

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Re: DDR2 chip how slow can you go?
« Reply #28 on: August 30, 2019, 07:49:45 pm »
16MB/s yes, but definitely not with fatfs. ;)
 

Offline SiliconWizard

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Re: DDR2 chip how slow can you go?
« Reply #29 on: August 30, 2019, 08:21:14 pm »
I would not use a FS for that. It would add overhead, possible bugs and make the wear-leveling much harder to do without largely modifying the FS code.
Just write your raw data in consecutive blocks, and cycle when you've reached the end of the available memory.
If you need to read that back on a computer, write a small utility - could be done with just a few lines of C or whatever language you feel comfortable with as long as you can get access to the raw data of the card. On Linux, you wouldn't even need to write anything: use dd. On Windows, could be done in under 100 lines of C, comments included.
« Last Edit: August 30, 2019, 08:23:23 pm by SiliconWizard »
 

Offline Yansi

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Re: DDR2 chip how slow can you go?
« Reply #30 on: August 30, 2019, 08:27:33 pm »
SDcard is already a managed NAND flash memory, isn't it? No wear leveling and bad block management required (the latter probably even not possible with an SDcard, as I think the ECC spare area sectors are not accessible? and the SDcard controller does all that required).

Bare metal NAND FLASH chip may be a completely different story.

//On windows, you use for example HXD.
 

Offline nctnico

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Re: DDR2 chip how slow can you go?
« Reply #31 on: August 30, 2019, 08:34:49 pm »
I would not use a FS for that. It would add overhead, possible bugs and make the wear-leveling much harder to do without largely modifying the FS code.
Most SD-cards from sensible brands will do wear levelling. Otherwise the flash would wear out very fast for the area where the FAT is written to.
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Offline SiliconWizard

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Re: DDR2 chip how slow can you go?
« Reply #32 on: August 30, 2019, 08:41:37 pm »
SDcard is already a managed NAND flash memory, isn't it? No wear leveling and bad block management required

Maybe you're right. Don't know how effective it is or if all SD cards are born equal (I would suspect not...)

Even if it's not for wear leveling, one benefit of writing data explicitely to consecutive sectors instead of writing it always starting at the same sector would be the ability to read back several past data blocks instead of just one. If you keep writing from the first sector, the SD card controller may write the data in different parts of the Flash for wear leveling, but you will never be able to access anything else but the last block.
 

Offline Kilrah

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Re: DDR2 chip how slow can you go?
« Reply #33 on: August 30, 2019, 08:45:10 pm »
Most SD-cards from sensible brands will do wear levelling. Otherwise the flash would wear out very fast for the area where the FAT is written to.
I don't know of any commercial card that does this, and yes the FAT area is what usually fails first for obvious reasons.
SOME industrial spec ones do it, but they're a niche and specifically marketed as such.
 

Offline JohanHoltbyTopic starter

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Re: DDR2 chip how slow can you go?
« Reply #34 on: August 30, 2019, 10:20:36 pm »
I'm a test energier and this memory will be in a switch module which will be one of my products I will sell to my clients. It's a modular system of startkabel modules. Each sub module will ha ve 40 channels 32 in from TPs and 8 out (to the 8 rows). Each connection will have monitoring for safety and debugging for current and voltage. I want to have the data for all channels for the last 8 seconds. So when the test is stoped then I can go around and check what happens leading up to the break in the system to know what's happening and why. No more reruns to try to find the problems so streaming is not needed. No more broken equipment du to malfunctioning DUTs since the system can set the safty levels for each value. The STM32 chip has 4ADC with 5Msps each.

Regarding my lack of knowledge I have to agree on this topic since I have not worked with any other memory modules than EEPROMs and SD cards. The layout and exact schematics will be done by a small design house which have good knowledge of high speed communication but as some pointed out I need to know what I want ;).

When I did look in to the Flash modules I noticed that I will need to replace the SD cards two times every year for a 128Gb SD card. And since this system will be deployed by an EMS overseas often I don't have the luxury of replacing SD cards. SO about 10 years of operation would be great.

So right now I hink of going with SDRAM or SRAM.
 

Offline SiliconWizard

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Re: DDR2 chip how slow can you go?
« Reply #35 on: August 30, 2019, 10:48:07 pm »
OK now that's clearer. I agree in your case RAM would make a lot more sense.

SDRAM would be the way to go IMO. Take a look there: http://www.issi.com/US/product-dram-SDR.shtml
For the same memory size with SRAM, you'll need quite a few ICs and that will cost you an arm and a leg.
 
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Offline JohanHoltbyTopic starter

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Re: DDR2 chip how slow can you go?
« Reply #36 on: August 30, 2019, 10:52:26 pm »
IOW: use a cheap FPGA (Xilinx Spartan series for example) to read a bunch of ADCs and stream the data into a PC using PCIexpress.  Inside the PC you'll have easy access to (fast) data storage and analysis.

This is an interesting point and I will probably go this rout to extract the data from the system but not by live streaming since the system might have up to 8 boards in each stacks and up to 16 stacks and each board will have 80 1Msps data streams (1Msps per adc channel).
That would be about 10 gigabytes (not bit) per second.

The BOM cost per board my not be above 400 dollars or it will be hard to sell to the end customer. Is that inside an arm and an leg? If not I will need to limit the amount of memory.
 

Offline SiliconWizard

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Re: DDR2 chip how slow can you go?
« Reply #37 on: August 30, 2019, 10:56:59 pm »
IOW: use a cheap FPGA (Xilinx Spartan series for example) to read a bunch of ADCs and stream the data into a PC using PCIexpress.  Inside the PC you'll have easy access to (fast) data storage and analysis.

This is an interesting point and I will probably go this rout to extract the data from the system but not by live streaming since the system might have up to 8 boards in each stacks and up to 16 stacks and each board will have 80 1Msps data streams (1Msps per adc channel).
That would be about 10 gigabytes (not bit) per second.

The BOM cost per board my not be above 400 dollars or it will be hard to sell to the end customer. Is that inside an arm and an leg? If not I will need to limit the amount of memory.

Oh, for this amount you could definitely go for an external ADC+FPGA+DDR2 or DDR3 RAM... would cost you a lot less than an MCU+several big SRAM chips.
 

Offline JohanHoltbyTopic starter

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Re: DDR2 chip how slow can you go?
« Reply #38 on: August 30, 2019, 11:13:22 pm »
I will take a look in to that advice and investigate that stack. using a single FPGA would be nice since that would same som real estate which is not a luxury I have since I need to fit it all inside a standard test fixture. :)

The problem I did find before was that the ADC was very costly when they where not dedicated. An alternative would be using the STM32 with 4ADC ringing att 5Msps and use the 4 SPI channels at 18MBps to stream the data to the FPGA. Sure I would not get all the data there but I could limit the stored data frequency.
 

Offline nctnico

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Re: DDR2 chip how slow can you go?
« Reply #39 on: August 31, 2019, 12:23:42 am »
The ADCs inside a microcontroller may not be very good compared to a dedicated ADC chip. Especially in lower cost microcontrollers.
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Offline Yansi

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Re: DDR2 chip how slow can you go?
« Reply #40 on: August 31, 2019, 08:02:48 am »
IOW: use a cheap FPGA (Xilinx Spartan series for example) to read a bunch of ADCs and stream the data into a PC using PCIexpress.  Inside the PC you'll have easy access to (fast) data storage and analysis.

This is an interesting point and I will probably go this rout to extract the data from the system but not by live streaming since the system might have up to 8 boards in each stacks and up to 16 stacks and each board will have 80 1Msps data streams (1Msps per adc channel).
That would be about 10 gigabytes (not bit) per second.

The BOM cost per board my not be above 400 dollars or it will be hard to sell to the end customer. Is that inside an arm and an leg? If not I will need to limit the amount of memory.

Oh, for this amount you could definitely go for an external ADC+FPGA+DDR2 or DDR3 RAM... would cost you a lot less than an MCU+several big SRAM chips.

NOBODY did suggest SRAM, but there is a metric shit ton of microcontrollers with integrated SDRAM controllers, that can manage more than enough size of memory for his purpose and can deal with such data IO speeds without an issue.

FPGA of course is almost always more suitable option for large data ackq systems.
 

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Re: DDR2 chip how slow can you go?
« Reply #41 on: August 31, 2019, 06:16:52 pm »
Quote
The problem I did find before was that the ADC was very costly when they where not dedicated. An alternative would be using the STM32 with 4ADC ringing att 5Msps and use the 4 SPI channels at 18MBps to stream the data to the FPGA. Sure I would not get all the data there but I could limit the stored data frequency.
Define costly.

Assuming that you need simultaneous sampling (a reasonable assumption) then you have 10 USD (price of an STM32 with 3 channels) per 3 channels, giving you 3 USD per channel.

The cheapest 12 bit ADC I found on farnell was ~1 EUR in bulk quantities. Assuming you use several multichannel simultaneous sampling ADC as I have advised (or a fast ADC and a fast MUX), then you can cut down the price and improve performance.

Just because you are used to using STM32s doesn't mean that they are the best tool for everything. Just because you have a hammer does not mean everything is a nail.
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Offline OwO

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Re: DDR2 chip how slow can you go?
« Reply #42 on: August 31, 2019, 07:16:06 pm »
I would personally go with a Zynq based solution. Each FPGA board will cost ~$100 (if you use digikey prices) but has >2GB/s of memory bandwidth and up to 1GB of memory. The number of streams you can handle per board will only be limited by the available IOs.

The hard part is finding high channel count ADCs. I did a quick search on the analog devices website and couldn't find a suitable ADC (>=8 channels and >=1Msps per channel). Using an external MUX is very ugly in terms of timing (you'd need an analog switch that can switch on the order of 10MHz, and settle in a fraction of a cycle, which from what I'm aware does not exist at reasonable cost), so if I were tasked with this project I'd use my go-to technique which is delta sigma modulation using schmitt triggers.

The 74LVC14 contains 6 inverting schmitt triggers, each of which can implement a delta sigma modulator with only 2 resistors and a capacitor. I did spice simulations a while ago that showed this can work well well above 10MHz toggle frequency, so it should be adequate for your 1Msps signal. The output of each modulator is a single bit signal, which you would feed into the FPGA and use a CIC filter to decimate to 1Msps. The IO utilization would be one FPGA IO per stream, so it should be possible to do over 80 streams on a Zynq 7010. The CIC filters are very small and it's easy to implement a multi-channel filter that can handle 200 1Msps streams running at 200MHz.
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Offline NiHaoMike

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Re: DDR2 chip how slow can you go?
« Reply #43 on: September 01, 2019, 05:11:34 am »
There's even a trick to use the LVDS inputs on a FPGA as ADCs, of course you'll have to characterize it yourself.
https://hackaday.com/2015/09/09/video-fpga-with-no-external-ad/
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Offline JohanHoltbyTopic starter

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Re: DDR2 chip how slow can you go?
« Reply #44 on: September 01, 2019, 09:10:22 am »
I'm no fanboy of STM32 so I'm open to every thing. The reason I'm looking in to STM32 is that they have the F3 series which some of them have 4 ADCs running att 5Msps and can do scanning of multiple channels so in theory giving me about 20Msps but in reality some number less. As someone mentioned before they also have FSMC.

So after some more design thinking maybe going with a simple STM32F303CBT6 (2.7$ @ 1000 units) and do only two channels scanning which would give me 8ch. Using the SPI would be a working solution but I think the better solution would be to just push out new data using I/O pins. 16 pin wide bit banged parallell port to an FPGA. If I run in to problems I could also do differential signaling on the parallel port since they also come in higher pin count. Sure I might need to lower some specification if I run out of CPU cycles. Since I will have 20Mb/us and only 72 cycles to do it on. But in reality it will be just read data and push it to the FPGA. The FPGA could then be responsible for turning on and off the and storing the data to an DDR memory.

Regarding Zynq 7010 it looks interesting. I have not done any FPGA work before but dome some in school and liked it back then. How hard can it be ;) ....haha. Will post some new question on what FPGA to choose.

IOW: use a cheap FPGA (Xilinx Spartan series for example) to read a bunch of ADCs and stream the data into a PC using PCIexpress.  Inside the PC you'll have easy access to (fast) data storage and analysis.

What interface do you use for the PCIexpress? Standard parallel port or just and I/O board? To be able to dump all the data from every node for the last 8 seconds for every time a DUT fails is a hope I have but that is a lot of data in worst case and even with only 100-300 nodes (average simple sized test) that is about 2.5Gbyte of data and I can not bloc the test for more than maybe 5 seconds. So high speed to the PC would be nice.
 

Offline GeorgeOfTheJungle

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Re: DDR2 chip how slow can you go?
« Reply #45 on: September 01, 2019, 09:21:45 am »
When I did look in to the Flash modules I noticed that I will need to replace the SD cards two times every year for a 128Gb SD card. And since this system will be deployed by an EMS overseas often I don't have the luxury of replacing SD cards. SO about 10 years of operation would be great.

16 MB/s are 16*3600*24*365/1024 ~= 500 TB/year IIANM. That's almost 250000/128 ~= 2000 full card rewrites/erases in six months. An SD card can really handle that much?

There are now 256 and 512GB cards. If you've got spare pins or SD card interfaces in the STMs perhaps you could devise a RAID-ish setup with more than one card.
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Offline Yansi

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Re: DDR2 chip how slow can you go?
« Reply #46 on: September 01, 2019, 10:05:03 am »
Spare SDIO interfaces should not be required, SDIO I think supports multiple device interfacing. Never tried it though.

I still think this project is poorly thought out and the goal is not clear.
 

Offline JohanHoltbyTopic starter

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Re: DDR2 chip how slow can you go?
« Reply #47 on: September 01, 2019, 10:40:11 am »
I still think this project is poorly thought out and the goal is not clear.

Interested (with a true open mind, not aiming for protecting my darling) in what you think is the poor parts and do you have any suggestions? In the end I want this to be as a good product as it possible could be.

To give some more background:
Normally I get a limited test specification which are updated many times so there for I enjoy wokring with matrix based interface systems (TPs, instruments and PS on columns and they can be switched in by software to a number of shared rows e.g. PXI-2533) which enable only software updates as the product specification updates as long as the TPs stay in place.
However DUTs break and people make mistakes so debugging and safety is important. This leads to multiple reruns to find bugs and broken equipment in worst case. To avoid reruns I want an all seeing scope which can log all current and voltage going through the matrix. Whenever any thing breaks I want the matrix to trigger if e.g. a current is above set value and disconnect the switch.

Since the specifications is not set ahead of time I want to have it modular so that it will be able to connect and disconnect modules depending on specification changes. And since test systems is almost always one offs making custom PCBs are very costly in regards to labor cost.

Yansi with that background what would you suggest?
 

Offline Yansi

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Re: DDR2 chip how slow can you go?
« Reply #48 on: September 01, 2019, 01:16:26 pm »
I am still quite confused, as what the design goal of your instrument should be.  Have you posted a full definition of it? I do not follow the thread carefully, I may have missed. It even seems the design goal is changing throughout.

What I would like to see is something like this:

State the intention of the device, the typical end use (for us, who are not familiar for example with those PXI systems mentioned which)
State the desired electrical interfaces, bot inputs and outputs and its characteristics:

ie.: I need to record 32 analog voltage channels at 1Msps rate @12bit resolution and sample them simultaneously for whatever the reason. I need to record all channels for as long as 1 minute, and then read out the sampled values from the device through XYZ interface.

 
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Offline T3sl4co1l

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Re: DDR2 chip how slow can you go?
« Reply #49 on: September 01, 2019, 01:35:02 pm »
Why would you even consider an STM over, say, a multicore SOM, using USB or PCIe (and bridges, interfaces, FPGAs, etc. as needed) to concentrate data from the various peripherals?

Such a device also trivially(?) runs Linux, communicates over Ethernet, connects to the Internet, connects ordinary HID devices, HDMI or DVI or whatever monitors, etc.  In short, a small PC with custom hardware attached.

Timing constraints for test equipment usually isn't terribly tight (i.e., on a similar scale as toggling relays), so the relatively poor timing of a multitasking OS is fine; real-time functionality is still available, with some difficulty (run as root? timing still subject to device drivers and hardware timing?), but preferably all hard real-time activity should be constrained to the peripherals themselves, and merely buffered data flows to the PC.

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