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DDR2 chip how slow can you go?
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Yansi:

--- Quote from: SiliconWizard on August 30, 2019, 10:56:59 pm ---
--- Quote from: JohanHoltby on August 30, 2019, 10:52:26 pm ---
--- Quote from: nctnico on August 30, 2019, 07:14:54 pm ---IOW: use a cheap FPGA (Xilinx Spartan series for example) to read a bunch of ADCs and stream the data into a PC using PCIexpress.  Inside the PC you'll have easy access to (fast) data storage and analysis.

--- End quote ---

This is an interesting point and I will probably go this rout to extract the data from the system but not by live streaming since the system might have up to 8 boards in each stacks and up to 16 stacks and each board will have 80 1Msps data streams (1Msps per adc channel).
That would be about 10 gigabytes (not bit) per second.

The BOM cost per board my not be above 400 dollars or it will be hard to sell to the end customer. Is that inside an arm and an leg? If not I will need to limit the amount of memory.

--- End quote ---

Oh, for this amount you could definitely go for an external ADC+FPGA+DDR2 or DDR3 RAM... would cost you a lot less than an MCU+several big SRAM chips.

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NOBODY did suggest SRAM, but there is a metric shit ton of microcontrollers with integrated SDRAM controllers, that can manage more than enough size of memory for his purpose and can deal with such data IO speeds without an issue.

FPGA of course is almost always more suitable option for large data ackq systems.
daqq:

--- Quote ---The problem I did find before was that the ADC was very costly when they where not dedicated. An alternative would be using the STM32 with 4ADC ringing att 5Msps and use the 4 SPI channels at 18MBps to stream the data to the FPGA. Sure I would not get all the data there but I could limit the stored data frequency.

--- End quote ---
Define costly.

Assuming that you need simultaneous sampling (a reasonable assumption) then you have 10 USD (price of an STM32 with 3 channels) per 3 channels, giving you 3 USD per channel.

The cheapest 12 bit ADC I found on farnell was ~1 EUR in bulk quantities. Assuming you use several multichannel simultaneous sampling ADC as I have advised (or a fast ADC and a fast MUX), then you can cut down the price and improve performance.

Just because you are used to using STM32s doesn't mean that they are the best tool for everything. Just because you have a hammer does not mean everything is a nail.
OwO:
I would personally go with a Zynq based solution. Each FPGA board will cost ~$100 (if you use digikey prices) but has >2GB/s of memory bandwidth and up to 1GB of memory. The number of streams you can handle per board will only be limited by the available IOs.

The hard part is finding high channel count ADCs. I did a quick search on the analog devices website and couldn't find a suitable ADC (>=8 channels and >=1Msps per channel). Using an external MUX is very ugly in terms of timing (you'd need an analog switch that can switch on the order of 10MHz, and settle in a fraction of a cycle, which from what I'm aware does not exist at reasonable cost), so if I were tasked with this project I'd use my go-to technique which is delta sigma modulation using schmitt triggers.

The 74LVC14 contains 6 inverting schmitt triggers, each of which can implement a delta sigma modulator with only 2 resistors and a capacitor. I did spice simulations a while ago that showed this can work well well above 10MHz toggle frequency, so it should be adequate for your 1Msps signal. The output of each modulator is a single bit signal, which you would feed into the FPGA and use a CIC filter to decimate to 1Msps. The IO utilization would be one FPGA IO per stream, so it should be possible to do over 80 streams on a Zynq 7010. The CIC filters are very small and it's easy to implement a multi-channel filter that can handle 200 1Msps streams running at 200MHz.
NiHaoMike:
There's even a trick to use the LVDS inputs on a FPGA as ADCs, of course you'll have to characterize it yourself.
https://hackaday.com/2015/09/09/video-fpga-with-no-external-ad/
JohanHoltby:
I'm no fanboy of STM32 so I'm open to every thing. The reason I'm looking in to STM32 is that they have the F3 series which some of them have 4 ADCs running att 5Msps and can do scanning of multiple channels so in theory giving me about 20Msps but in reality some number less. As someone mentioned before they also have FSMC.

So after some more design thinking maybe going with a simple STM32F303CBT6 (2.7$ @ 1000 units) and do only two channels scanning which would give me 8ch. Using the SPI would be a working solution but I think the better solution would be to just push out new data using I/O pins. 16 pin wide bit banged parallell port to an FPGA. If I run in to problems I could also do differential signaling on the parallel port since they also come in higher pin count. Sure I might need to lower some specification if I run out of CPU cycles. Since I will have 20Mb/us and only 72 cycles to do it on. But in reality it will be just read data and push it to the FPGA. The FPGA could then be responsible for turning on and off the and storing the data to an DDR memory.

Regarding Zynq 7010 it looks interesting. I have not done any FPGA work before but dome some in school and liked it back then. How hard can it be ;) ....haha. Will post some new question on what FPGA to choose.


--- Quote from: nctnico on August 30, 2019, 07:14:54 pm --- IOW: use a cheap FPGA (Xilinx Spartan series for example) to read a bunch of ADCs and stream the data into a PC using PCIexpress.  Inside the PC you'll have easy access to (fast) data storage and analysis.

--- End quote ---

What interface do you use for the PCIexpress? Standard parallel port or just and I/O board? To be able to dump all the data from every node for the last 8 seconds for every time a DUT fails is a hope I have but that is a lot of data in worst case and even with only 100-300 nodes (average simple sized test) that is about 2.5Gbyte of data and I can not bloc the test for more than maybe 5 seconds. So high speed to the PC would be nice.
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