Electronics > Projects, Designs, and Technical Stuff
DDR2 chip how slow can you go?
Berni:
--- Quote from: JohanHoltby on September 01, 2019, 10:40:11 am ---
--- Quote from: Yansi on September 01, 2019, 10:05:03 am ---I still think this project is poorly thought out and the goal is not clear.
--- End quote ---
Interested (with a true open mind, not aiming for protecting my darling) in what you think is the poor parts and do you have any suggestions? In the end I want this to be as a good product as it possible could be.
To give some more background:
Normally I get a limited test specification which are updated many times so there for I enjoy wokring with matrix based interface systems (TPs, instruments and PS on columns and they can be switched in by software to a number of shared rows e.g. PXI-2533) which enable only software updates as the product specification updates as long as the TPs stay in place.
However DUTs break and people make mistakes so debugging and safety is important. This leads to multiple reruns to find bugs and broken equipment in worst case. To avoid reruns I want an all seeing scope which can log all current and voltage going through the matrix. Whenever any thing breaks I want the matrix to trigger if e.g. a current is above set value and disconnect the switch.
Since the specifications is not set ahead of time I want to have it modular so that it will be able to connect and disconnect modules depending on specification changes. And since test systems is almost always one offs making custom PCBs are very costly in regards to labor cost.
Yansi with that background what would you suggest?
--- End quote ---
Ah now i get it what you are trying to do.
In terms of that i have two suggestions depending on the response time needed.
1) Near instantanious response time:
Just connect a bunch of ADCs to a FPGA and build a standard data analysis block inside it. Each ADC channel feeds its own data analysis block that on the fly measures a bunch of parameters about the input waveform. Then have another block constantly do a comparison of those values against some configured min/max ranges, if it goes out of range the FPGA can signal it in a matter of nanoseconds to the outside so that you switch whatever you needed to switch.
2) Milisecond range response time:
Grab something like a FTDIs USB3.0 FIFO chip ( FT600/FT601 ) and use a little bit of CPLD glue logic to connect it to a bunch of ADCs. As soon as you give it power it simply starts streaming the ADC data out to the USB host and that's all it does, no configuration or anything. Then you plug this into a small PC running windows or a single board computer running linux where you write your software to take in the data, analyze it and then send a command to switch whatever you need via any means you like: Serial, USB, Ethernet, SCPI etc... The advantage here is that you have gigabytes of RAM available to buffer it or at these speeds the data can easily be directly written to the hard drive giving you terabytes of recording memory. There is as much processing power as you would ever need (Heck you can use Cuda for GPU acceleration even) but the response times are going to be much slower due to all the extra stuff in the loop and the OS scheduler getting in the way.
As for cheap high speed ADCs you can find 16bit ADCs that run from a megasample to >100 MSPS for a reasonable price in the form of CCD imaging digitizers (Used to turn signals from a CCD chip into digital pixels). The only problem is that these ADCs often have weird interfaces buses or LVDS and things like that to talk to them, so running them using a MCU is very annoying, but easy with a FPGA.
JohanHoltby:
The FPGA rout will be best since storing the data locally is important. USB is not an option since It's not a stable protocol for production environment. I will make a new thread with more structured specifications. I have got what I was asking for (and a lot more :)) and now feel more comfortable with the decision FPGA -> DDR [2 or3] for storing the data. Hacking is not an good option.
Thank you all for your help!
Yansi:
So why did you begin yourself, with bold statements of hacking a DDR memory? (... ... see those shifting goals?)
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