EEVblog Electronics Community Forum
Electronics => Projects, Designs, and Technical Stuff => Topic started by: jeffr on March 14, 2016, 11:44:05 am
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Hi All,
My PCB uses 800 MHZ DDR2 memory.
I'm calculating a single ended trace impedance of 80 Ohms for my PCB. The data sheet calls for 50 Ohms.
Will placing 80 Ohm parallel termination resistors to the address lines and adjusting the ODT for 75 Ohms for the data lines achieve the right impedance?
Cheers!
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Why you don't modify trace width or stackup to make it 50 ohms though?
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Hi All,
My PCB uses 800 MHZ DDR2 memory.
I'm calculating a single ended trace impedance of 80 Ohms for my PCB. The data sheet calls for 50 Ohms.
Will placing 80 Ohm parallel termination resistors to the address lines and adjusting the ODT for 75 Ohms for the data lines achieve the right impedance?
Cheers!
Hi
Don't forget to modify the driver ends of the lines to work with your higher impedance. After you have done that, re-run timing closure on all the parts at the new operating point.
Will it work / will in not work? Without a full analysis, you are just rolling dice. Sometimes you win sometimes you don't win.
Bob
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Why you don't modify trace width or stackup to make it 50 ohms though?
Hi. My fabricator's stackup is set. I don't think I can modify it.
The parts I use are BGA. If I make the traces wider I can't route them between the pads.
Are there ways to get around that? If I make the neck of the trace thinner (80 Ohms) but the majority of the trace wider (50 Ohms) what becomes the trace's impedance now?
Hi
Don't forget to modify the driver ends of the lines to work with your higher impedance. After you have done that, re-run timing closure on all the parts at the new operating point.
Will it work / will in not work? Without a full analysis, you are just rolling dice. Sometimes you win sometimes you don't win.
Bob
Thanks Bob. Are there tools for full analysis for a PCB?
To make sure, the termination resistor should be the same value as the trace impedance?
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Why you don't modify trace width or stackup to make it 50 ohms though?
Hi. My fabricator's stackup is set. I don't think I can modify it.
The parts I use are BGA. If I make the traces wider I can't route them between the pads.
Are there ways to get around that? If I make the neck of the trace thinner (80 Ohms) but the majority of the trace wider (50 Ohms) what becomes the trace's impedance now?
Hi
Don't forget to modify the driver ends of the lines to work with your higher impedance. After you have done that, re-run timing closure on all the parts at the new operating point.
Will it work / will in not work? Without a full analysis, you are just rolling dice. Sometimes you win sometimes you don't win.
Bob
Thanks Bob. Are there tools for full analysis for a PCB?
To make sure, the termination resistor should be the same value as the trace impedance?
Hi
There are indeed packages that will do a very full analysis of a PCB. There are even some that will tie that into the chip timing data that you need to use as well. That of course *assumes* the DRAM guys will give you the files you need to put into that program. You then need to bump all that data up with the fine grain timing on the FPGA. You may / may not be able to fiddle the FPGA to get it all to work. Since you *only* have control on the FPGA that's where it all has to happen.
Bob
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To make sure, the termination resistor should be the same value as the trace impedance?
Yes they should be the same value. With higher impedance your signals will be more susceptible to noise pickup so to compensate add some extra clearance between the traces if you can and it will probably work.
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If I make the neck of the trace thinner (80 Ohms) but the majority of the trace wider (50 Ohms) what becomes the trace's impedance now?
If you keep your neck length short (e.g. <100mils), you will be okay. This is common even for much faster designs, like DDR3-2133 etc.
Keep your reference plane uniform and continuous under your tracks. It's hard to suggest anything more defined without seeing layout.
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My PCB uses 800 MHZ DDR2 memory.
But what is the clock frequency of the interface? If you are in the 200 MHz range then you don't have to pay too much attention to signal integrity and impedance matching. For multi-MHz professional DDR2 boards you really should simulate the SI to see what happens with the various ODT and trace impedance configurations.
https://www.mentor.com/pcb/events/analyzing-ddr2-3-4-memory-interfaces--guarantee-your-margins-before-you-build-and-ship-boards (https://www.mentor.com/pcb/events/analyzing-ddr2-3-4-memory-interfaces--guarantee-your-margins-before-you-build-and-ship-boards)
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My PCB uses 800 MHZ DDR2 memory.
But what is the clock frequency of the interface? If you are in the 200 MHz range then you don't have to pay too much attention to signal integrity and impedance matching. For multi-MHz professional DDR2 boards you really should simulate the SI to see what happens with the various ODT and trace impedance configurations.
https://www.mentor.com/pcb/events/analyzing-ddr2-3-4-memory-interfaces--guarantee-your-margins-before-you-build-and-ship-boards (https://www.mentor.com/pcb/events/analyzing-ddr2-3-4-memory-interfaces--guarantee-your-margins-before-you-build-and-ship-boards)
Hi
An equally important set of questions would be:
Are we talking about 12" traces or 0.12" traces?
Is this FR-4 board and if so how did you come up with the Er numbers?
How well are the traces matched?
How close is the interface device (other end of the wires to the memory) to maxed out?
Lots of variables .
Bob
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Hi,
I would suggest to see if the memory manufacturer or the CPU manufacturer has some design guidelines.
Here is one guideline that describes DDR2 https://www.altera.com/ja_JP/pdfs/literature/an/an408.pdf (https://www.altera.com/ja_JP/pdfs/literature/an/an408.pdf)
I have used Saturn PCB for to calculate trace impedance.
I had a similar problem once with a LPDDR2 memory. There I made the traces little less wide at the BGA pins so that the traces could be routed out. And immediately when possible then I used normal trace width. The traces needed to be quite wide due to the PCB buildup.
Here are some things that I see as most important:
-Impedance
-All traces length matched
-Differential signals routed
-No split planes under or over the traces.
-Termination according to the datasheet.
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Thanks for the inputs.
A DDR2 memory IC will be run with clock frequency 400 MHZ for 800 MHZ DDR between a Spartan 6 FPGA thats 2'' away.
Using 4 layer FR408 board Er 3.66 for 1GHZ.
1.4 mil copper thickness. 6.7 mil thick FR408 between top and second layer.
Online microstrip impedance calculator gives estimate for 49 Ohms impedance for 12 mil trace width and 56 Ohms impedance for 10 mil trace width.
5 mil trace fits between BGA pads but is 80 Ohms.
Target impedance defined by Micron guideline TN4720 is 40 to 55 Ohms for "reduced drive".
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I think you will need more layers.
This document can give helpful information about layers and stackups.
http://www.icd.com.au/articles/Stackup_Planning_AN2011_2.pdf (http://www.icd.com.au/articles/Stackup_Planning_AN2011_2.pdf)
The LPDDR2 board that i routed had 10 layers. And I would remember that I needed 3 inner layers for the memory signals.
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Thanks for the inputs.
A DDR2 memory IC will be run with clock frequency 400 MHZ for 800 MHZ DDR between a Spartan 6 FPGA thats 2'' away.
Using 4 layer FR408 board Er 3.66 for 1GHZ.
1.4 mil copper thickness. 6.7 mil thick FR408 between top and second layer.
Online microstrip impedance calculator gives estimate for 49 Ohms impedance for 12 mil trace width and 56 Ohms impedance for 10 mil trace width.
5 mil trace fits between BGA pads but is 80 Ohms.
Target impedance defined by Micron guideline TN4720 is 40 to 55 Ohms for "reduced drive".
Hi
What does the rest of the stack up look like?
If you have a symmetric stack up on the board, you have 6.7 mils between layers 3 and 4. Unless the overall board is unusually thin, you have a very large core between layers 2 and 3. Why does this matter?
Your traces only count as "constant impedance" if they run over a solid plane. If layer 2 is solid ground, then layer 3 is a *long* ways away for doing anything else on.
Bob
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Thanks for the inputs.
A DDR2 memory IC will be run with clock frequency 400 MHZ for 800 MHZ DDR between a Spartan 6 FPGA thats 2'' away.
Using 4 layer FR408 board Er 3.66 for 1GHZ.
1.4 mil copper thickness. 6.7 mil thick FR408 between top and second layer.
Online microstrip impedance calculator gives estimate for 49 Ohms impedance for 12 mil trace width and 56 Ohms impedance for 10 mil trace width.
5 mil trace fits between BGA pads but is 80 Ohms.
Target impedance defined by Micron guideline TN4720 is 40 to 55 Ohms for "reduced drive".
Sounds like the OSHPark 4-layer board:
http://docs.oshpark.com/services/four-layer/ (http://docs.oshpark.com/services/four-layer/)
It has a massive core between layers 2-3, so unless both layers 2 and 3 are ground, you can only run these controlled impedance lines on the top layer.
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Thanks for the inputs.
A DDR2 memory IC will be run with clock frequency 400 MHZ for 800 MHZ DDR between a Spartan 6 FPGA thats 2'' away.
Using 4 layer FR408 board Er 3.66 for 1GHZ.
1.4 mil copper thickness. 6.7 mil thick FR408 between top and second layer.
Online microstrip impedance calculator gives estimate for 49 Ohms impedance for 12 mil trace width and 56 Ohms impedance for 10 mil trace width.
5 mil trace fits between BGA pads but is 80 Ohms.
Target impedance defined by Micron guideline TN4720 is 40 to 55 Ohms for "reduced drive".
Sounds like the OSHPark 4-layer board:
http://docs.oshpark.com/services/four-layer/ (http://docs.oshpark.com/services/four-layer/)
It has a massive core between layers 2-3, so unless both layers 2 and 3 are ground, you can only run these controlled impedance lines on the top layer.
Hi
Well, then it's time to head off to another supplier. The alternative is to simply ignore the problem and hope it all works. There will be a bunch of "eye tuning" of the final design anyway with the parts being used.
Bob