DDR3 VTT termination routing and bit swapping?

[Northy]

Does anyone have much experience connecting a single DDR3 to a processor?

I've got a couple of questions:

I'm looking at the routing on an evaluation board, the DDR3 is on the top of the board, the VTT termination resistors are on the bottom of the board but outside the via field required for the DDR3 BGA. The routing between the DDR3 and processor is on internal layers, so the routing from the DDR3 vias to the VTT termination resistors essentially create 'stubs' on the bottom of the board. These 'stubs' seem to be matched length on the evaluation board. Would this be the best/most correct way to do this - even though all routing guidelines says to not create stubs.

There has been some bit swapping of some of the data lines. I've found a couple of references online to this being a via solution to improve routing, but no description on why it actually works. Is it simply that whatever data you write out to the memory will come back as it was written out, even though it was stored differently on the memory.
For example, write out: 01010101 but at the other end of the data lines (at the memory) its: 01101100 due to bit swapping, but that doesn't matter because when you read it back it actually comes back as it was written out? 

Thanks,

G

[TomS_]

Re bit swapping, that is exactly what I understand.

For simple data storage, the RAM and processor have no knowledge, nor need they even care, about the order of the bits. What ever you write to the RAM is what you are going to read back because everything still maps 1:1.

It would matter (if DDR RAMs have such features) if you were to read vendor/part IDs or status words, or write configuration words to the RAMs - you'll need to rearrange the bits to match what the device provides/expects.

[langwadt]

back in the day even data and address lines on eproms were sometimes scrambled to make routing easier, the content of the eprom just had to be scrambled to same way before programming

[Hydron]

IIRC (and based on earlier dram generations) you can mess with the data bit order without issues, but not the address bits. Should be easy enough to confirm - it's not unusual to want to ease layout this way.

[langwadt]

IIRC (and based on earlier dram generations) you can mess with the data bit order without issues, but not the address bits. Should be easy enough to confirm - it's not unusual to want to ease layout this way.

as soon as the memory isn't just a simple big linear block, but has pages, sectors or it has commands you need to pay attention

[Hydron]

IIRC (and based on earlier dram generations) you can mess with the data bit order without issues, but not the address bits. Should be easy enough to confirm - it's not unusual to want to ease layout this way.

as soon as the memory isn't just a simple big linear block, but has pages, sectors or it has commands you need to pay attention

This is why I suggested that address bits cannot be messed with - they are what carry the commands. A quick google search (which I suggest the OP does independently) suggests that some bit swapping is indeed possible with DDR3, albeit with certain rules to follow.

[Northy]

Thanks for the replies so far 

Does anyone have any feelings about VTT termination and stubs?

This is why I suggested that address bits cannot be messed with - they are what carry the commands. A quick google search (which I suggest the OP does independently) suggests that some bit swapping is indeed possible with DDR3, albeit with certain rules to follow.

I did google the topic before posting here and all I could find was statements like 'you can swap the bits', I'm just really keen on understanding why it's ok to swap the bits - how it actually works. This I could not find.

Thanks,

G

[sd]

Regarding swapping bits, it's exactly how you described it in your first post.
There are some limitations though, like not swapping the lowest bit in a byte lane, if the CPU uses hardware write leveling. You can usually swap byte lanes as well, but read the CPU's datasheet.

As for the other point, not sure what you mean by stubs. The address/control signals don't have on die termination on the DDR IC.

[Northy]

Regarding swapping bits, it's exactly how you described it in your first post.
There are some limitations though, like not swapping the lowest bit in a byte lane, if the CPU uses hardware write leveling. You can usually swap byte lanes as well, but read the CPU's datasheet.

Thanks 

As for the other point, not sure what you mean by stubs. The address/control signals don't have on die termination on the DDR IC.

Correct, they don't, and it seems the recommended termination type is VTT termination.
I've attached a shot from the gerbers of an AD evaluation board showing the resistor packs and the traces to the DDR3 vias. Aren't these essentially creating stubs? Which is one thing guides tell you not to do on these lines?

G

[sd]

Those aren't stubs. The only stub here would be part of the via, the DDR pad, ball and the IC.

[Northy]

Those aren't stubs. The only stub here would be part of the via, the DDR pad, ball and the IC.

I've just been doing more research over the last couple of hours, I guess they aren't stubs as they are the continuation of the track onto the termination resistors.
I guess it's important to length match them too then as shown?

Thanks,
G

[PeteH]

"Flyby" DDR3 routing - very standard practice to tap off address to each DDR3 part and put the terminations at the last DDR3 chip.

Flight times (pin to pin delays,.controller to each DDR3 IC) should be phase matched (tolerance comes from the controller's datasheet) but the distance to the terminations can be less controlled. Usually easy enough to place resistors to minimize lengths, don't need to tune to those terminations.

[Northy]

"Flyby" DDR3 routing - very standard practice to tap off address to each DDR3 part and put the terminations at the last DDR3 chip.

Flight times (pin to pin delays,.controller to each DDR3 IC) should be phase matched (tolerance comes from the controller's datasheet) but the distance to the terminations can be less controlled. Usually easy enough to place resistors to minimize lengths, don't need to tune to those terminations.

Hi Pete,

I'm back on this routing again.

Are you saying a I should keep the routing to the termination resistors as short as possible, but also match the length as best I can? Would you have a 'gut feel, ballpark' figure for how well they need to be matched?

Thanks,
G