EEVblog Electronics Community Forum
Electronics => Projects, Designs, and Technical Stuff => Topic started by: D Straney on December 06, 2024, 04:58:18 pm
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Thought it was time to do some more detailed reverse-engineering on the various ceramic hybrid modules I've opened: (https://www.flickr.com/photos/147639706@N02/albums/72177720313121991/)
Analog Devices HTS-0010SD Track and Hold
(https://live.staticflickr.com/65535/53602644021_4a5e239372_c.jpg) (https://flic.kr/p/2pEFyzB)
(https://live.staticflickr.com/65535/53833736172_0fdfe83683_c.jpg) (https://flic.kr/p/2q26Ye3)
Here's the datasheet (https://www.analog.com/media/en/technical-documentation/obsolete-data-sheets/75613601HTS_0010.pdf).
This is a fairly high-speed "track and hold" (/ "sample and hold") circuit, which can rapidly sample an input waveform - commonly used as part of an analog-to-digital converter, or to downconvert a high-frequency signal for slower processing. This one has a bandwidth of 60 Mhz (17 ns period) but needs about a 10 ns sampling window for the output to settle within 1%, so the usable frequency for a sampling oscilloscope, for example, would be more in the single-digit-Mhz range.
Here's how the internal components are divided up, and the complete schematic I traced from a microscope photo:
[attachimg=1]
[attachimg=2]
Most of the large squares are actually capacitors (two horizontal plates separated vertically by a thin dielectric), used for local filtering of the many power supplies.
Input buffer
This section buffers the incoming signal to drive the sampler. The signal drives two complementary sections, whose outputs are then re-combined by R7, to produce an output which can actively source and sink current. Having the sequential emitter-followers with an NPN followed by a PNP (and a PNP followed by an NPN) roughly cancels the DC offsets from each transistor's Vbe, if biased correctly. I wouldn't expect the linearity to be great, as the Vbe values would change depending on load current, but the datasheet shows 0.01% non-linearity for a 1V max. input: the low signal voltage compared to the supply voltage (small change in bias current) and low output current required due to small hold capacitor value & high-impedance output buffer must help a lot.
Sampling bridge
This is a standard 4-diode sampling bridge: I can't find any references that explain their basic operation well (Edit: RoGeorge mentioned an explanation on p.66 of this Tektronix appnote (https://www.davmar.org/TE/TekConcepts/TekSamplingCircuits.pdf)), but the idea is that you forward-bias all the diodes (with a current source) to turn them all on. Because the diodes are intentionally matched to each other, D1 and D4's forward voltages are roughly equal, and D2 and D3's forward voltages are roughly equal, so the output voltage at R9 & hold capacitor C6 follows the input voltage at R8. To turn off the "gate", you reverse-bias all the diodes, and now hold capacitor C6 is isolated from the input signal, and stores its voltage "indefinitely" (with practical limits).
Bridge driver
This section generates the forward-bias currents and reverse-bias voltages to rapidly switch the sampling bridge on and off, controlled by an ECL input. The one actual IC in this module is an ECL buffer (or gate with hard-wired input?), which accepts a single ECL input and generates complementary ECL outputs, to drive each side of the sampling bridge separately. (While on, the cathode-side D1/D4 voltage needs to be low, while the anode-side D2/D3 voltage needs to be high, to turn on the diodes, and vice versa for when the sampling bridge is off)
Q8 and Q11 serve as biasing for a pair of fixed current sinks (Q6 & Q7), and a pair of fixed current sources (Q9 & Q10). The two halves of Q5 (Q5A & Q5B) serve as switches for the current sinks. When Q5A is off, for example, Q9 sources current / connects a positive voltage to the top side of the sampling bridge. When Q5A turns on, it connects Q6, which now (presumably) sinks more current than Q9 is sourcing, and so overall sinks current / connects a negative voltage to the top side of the sampling bridge, instead.
The speed of the sampling bridge driver is a big limitation on the speed of the whole sampler, along with the properties of the sampling bridge diodes themselves, and so to get the most out of the sampler, the switching needs to happen quickly. The use of ECL and current sources throughout helps here because of...
1. No transistors are ever in saturation, which means that the "storage time", a significant typically-µs-scale delay when bringing a bipolar out of saturation (https://en.wikipedia.org/wiki/Bipolar_junction_transistor#Turn-on,_turn-off,_and_storage_delay), doesn't slow down switching.
2. The fixed currents, if set to sufficiently high values, rapidly charge or discharge the various parasitic capacitances at the switching nodes. This provides a simple "control knob" the designer can use for selecting a tradeoff between power consumption and switching speed.
This was the standard way of doing high-speed digital switching with bipolar transistors before fast MOSFETs and CMOS logic became common a decade or two later.
Q5 is a 5-transistor array, with the same pinout & arrangement as a CA3045/CA3046 (https://www.alldatasheet.com/html-pdf/66310/INTERSIL/CA3045/320/1/CA3045.html) or CA3086 (https://www.qsl.net/iw2grf/pdf/ca3086.pdf): 3 individual transistors, and 2 connected as a differential pair. However, surprisingly, only two of the 5 are actually used. I don't know why they didn't use a 2-transistor matched pair for this.
[attachimg=4]
Also, one mystery here is the DC behavior of the bridge driver. With AC-only coupling via C1 & C2, only short excursions from the default state (whether track, or hold) would be allowed, and I didn't see any mention of that in the datasheet. Also, the only valid states for the sampling bridge are with Q5A & Q5B in opposite states: having both halves of Q5 off when idle doesn't make any sense (although R15 might have something to do with that). I think what looks like capacitors here in the bridge driver (C1 & C2) might actually be diodes for level-shifting between the -5.2V of the ECL signals, and the -15V for the rest of the bridge driver. I can't come up with a diode configuration which actually makes sense though (even including Q5 being PNPs instead of NPNs).
Output buffer
Q12 is a JFET used to buffer the hold capacitor's value; a JFET is used here instead of a bipolar transistor because of its infinitesimal input leakage current drains the tiny hold capacitor's voltage much slower than a bipolar's base current would. After Q12A's buffering of the hold capacitor voltage, this drives a class-AB output stage with Q14 & Q15 creating an offset voltage to compensate for Q16 & Q19's Vbe, and create an appropriate DC collector current through Q16 & Q19 at zero voltage (to avoid excessive crossover distortion). Q12B and Q13 create a current sink to bias Q12A and Q14/Q15 at a constant current.
Just like the input buffer, with no feedback you'd expect the output buffer's linearity to suffer here as the Vbe values change with changing current, ruining the careful balancing act, and that's reflected by the datasheet. With a 1KΩ load on the output, harmonic distortion is listed as -68 dB, but with a much heavier 75Ω load, this drops to -50 dB. Honestly, these are still impressive numbers overall for such a simple circuit (esp. because this includes the distortion of the input buffer & sampling bridge), and this is not to criticize the design - just to illustrate the limitations and tradeoffs.
Here's Q12, a matched pair on a single die:
[attachimg=3]
Feedback
At first when tracing the circuit, I thought this might be some sort of compensation for various parasitic effects of the sampling bridge. However, on further study, this is actually a part of the bridge driver! Q17 and Q18 create a copy of the output voltage (and therefore, a copy of the hold capacitor voltage) at R10.
Remember how I said that the transistors in the bridge driver never were put into saturation? Without this section of the circuit, when the sampling bridge was turned off in "voltage mode" to reverse-bias the sampling diodes, both Q9 and Q7 would be in saturation: there's no path for collector current after charging the parasitic capacitances, and so their collector voltages would rise(/fall) past their base voltages. However, D5, D6, and R10 ensure that Q9 and Q10 always are in the active region by providing a path for their collector current, and limiting how far their collector voltages can rise or fall. R10 sets the reverse-bias voltage on D3 & D4, as (fixed current) x (resistance).
Closing
Finally, the weird silicon(?) resistors make for some interesting shapes:
[attachimg=5][attachimg=6][attachimg=7]
Let me know if you have any insights or questions.
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Clarification on the "feedback" section of the circuit:
D5, D6, and R10 make the sampling bridge's off-state voltages referenced to the hold capacitor voltage. The D1 & D4 cathodes will always be "X" volts above C6, and the D2 & D3 anodes will always be "Y" volts below C6, etc. with "X" & "Y" determined by the bridge driver's fixed current source & sink values multiplied by each half of R10.
Besides keeping Q9 & Q7 out of saturation, I think the biggest reason to do this is actually for the bridge's turn-off & off-state behavior. When the control voltages on the sampling bridge are flipped to reverse-bias D1-D4 and close the gate, the rising voltage on D4's cathode injects current into C6 through D4's parasitic capacitance. At the same time, the falling voltage on D3's anode pulls current out of C6 through D3's parasitic capacitance: a simple matter of dV/dt across a capacitor. C6 has a very small value, to allow it to sample the input signal quickly (short gate-opening times) and give it a large analog bandwidth (input buffer is limited in slewing a large capacitive load quickly), so these currents can introduce some serious error into the C6 voltage.
However, because the final D4-cathode and D3-anode voltages are fixed relative to C6's voltage, and D3 & D4 are the same type with the same parasitic capacitance characteristics, the total charge injected into C6 at turn-off through D4 is going to be almost exactly equal to the charge removed from C6 through D3. The two errors in opposite directions cancel out. Otherwise, if the final D4-cathode & D3-anode voltages were fixed at, let's say, +10V & -10V, it means that positive output voltages would see a consistent negative error (more charge removed by moving D3's anode a larger "distance" from Vout to -10V) and negative output voltages would see a consistent positive error (more charge injected by moving D4's anode a larger "distance" from Vout to +10V).
During the off-state, having equal reverse-bias voltages across D3 & D4 also means that the leakage currents through both of them will cancel out, therefore removing another source of error which would cause C6's voltage to drift over time. This is especially important with the Schottky diodes used in the sampling bridge: the tradeoff vs. plain P-N junction diodes is lower forward voltage and no reverse-recovery effects, for higher capacitance and higher leakage. The D5/D6/R10 "equal negative bias" scheme here takes care of both the capacitance & leakage effects all at once.
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I am surprised that it is not faster. The sampling time in this type of design is primarily limited by the RC delay of the driver and load capacitance.
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The 8518 label in the lid must be likely the date code?
Do you know where this track and hold device came from?
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The 8518 label in the lid must be likely the date code?
I agree, think that's right.
Do you know where this track and hold device came from?
An eBay batch of (unused) NOS parts, that this guy (https://www.instagram.com/evilmonkeyzdesignz/) got, and was kind enough to give one to me as part of a two-way duplicate swap. It's a standard COTS part, rather than anything application-specific. So I don't know exactly what specific pieces of equipment used this internally.
I am surprised that it is not faster. The sampling time in this type of design is primarily limited by the RC delay of the driver and load capacitance.
Me too! Especially with the ECL input I was expecting some couple-ns kinds of times. Thought it was interesting that they advertised the 5 ps jitter in the sample window timing, but the slow settling time and long sampling window needed make that less impressive in practice than it sounds - unless you're going for serious precision on a slower signal, like if building a precision multi-Mhz LVDT for some reason.
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Teledyne C66-1 Solid-State Relay
This comes in a metal can:
[attachimg=1]
Now with lid removed:
[attachimg=2]
There were a couple blobs of epoxy (one over the top-left electronics, and one over the top-right electronics) that I removed to get these photos. Removing the epoxy moved the wirebonds, so don't pay too much attention to where the wirebonds sit in the upper half.
[attachimg=3]
The output switching is done by the two big power transistors in the bottom half: these are arranged back-to-back, so that the body diodes never conduct at the same time, with a shared source connection that runs up the middle between them.
[attachimg=4]
These power MOSFET gates are driven optically. The isolated control side consists of two LEDs connected in series in the top-right corner (the two tiny squares), and these shine light on a photovoltaic array right next to them (the larger square). I'm not sure if the light is passed sideways across a small horizontal gap, or whether the light was diffused and reflected through the white epoxy blob (from LED top surface to PV top surface) to add horizontal electrical insulation.
The LEDs & mini solar cell generate a gate voltage to turn on the power MOSFETs, but the current these can produce is very low - discrete versions of PV isolators (https://www.digikey.com/en/products/detail/toshiba-semiconductor-and-storage/TLX9906-TPL-F/11568808) can only produce 10s of uA, from an LED current of 10s of mA. This charges the power MOSFET gate capacitance slowly, but multi-ms turn-on times or 10s-of-ms turn-on times are fine if you're just switching a load on and off, and not trying to do 100+ kHz switching for a power supply. However, this is a problem for turn-off: the pull-down resistor on the MOSFET gates, to discharge the gate voltage when the input drive voltage isn't present, needs to be large enough to avoid stealing all the turn-on current, but this makes the turn-off even slower than the turn-on.
[attachimg=5]
There's also an IC on the power side; I accidentally took a chip out of it with my knife while trying to carefully peel away the epoxy, so although it's pretty simple, I can't fully map the circuitry. This is probably responsible for some kind of "fast turn-off" function, to sense when the gate voltage starts to sag as the LEDs are turned off, and actively discharge the gate capacitances for a faster turn-off.
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TRT 3511.150.1351
I have no idea where this part was used; I just bought it as NOS from a random Polish eBay seller for a few $.
(https://live.staticflickr.com/65535/53495674827_86f22eef4c_z.jpg) (https://flic.kr/p/2pvejna)
(https://live.staticflickr.com/65535/53496865649_6593c63172_z.jpg) (https://flic.kr/p/2pvkqmz)
(https://live.staticflickr.com/65535/53496565496_0a4b752565_z.jpg) (https://flic.kr/p/2pviT8w)
There's only one type of IC used here:
(https://live.staticflickr.com/65535/53834636471_4a73c1d74e_z.jpg) (https://flic.kr/p/2q2bzRr)
Also you can see the laser-trimming marks in this photo, where notches were cut into the resistors (made out of resistive material printed or sputtered directly onto the ceramic substrate) to adjust their values.
If we zoom in on one, we can see that they look like the Zeptobars die shot of the TL072 dual op-amp (https://zeptobars.com/en/read/ST-TL072-JFET-dual-opamp). The butterfly-looking structures are the input JFETs, arranged in squares with paralleled devices diagonal from each other to do some first-order cancellation of thermal gradients across the die.
(https://live.staticflickr.com/65535/53834981084_6039ed806d_z.jpg) (https://flic.kr/p/2q2dmi3)
The actual circuitry is pretty simple:
[attachimg=1]
It holds...
- 3 copies of a filter circuit, each with 2 stages of a Sallen-Key low-pass filter (https://en.wikipedia.org/wiki/Sallen%E2%80%93Key_topology#Application:_low-pass_filter). Two of these filter blocks have identical resistor geometries, while one has different-shaped resistors (the one on the bottom-right in the photos above).
- A single stage of a Sallen-Key low-pass filter
- A non-inverting gain stage of +2 (judging by resistor geometry)
- 2 un-committed op-amps, with their connections broken out to the external pins
This is a strange collection of miscellaneous things. Where might this be used?
The TL072 / TL082 / similar parts only have a bandwidth of a few Mhz at most, so the filter corner frequencies should be in the 10s or 100s of kHz, or lower; no RF happening here. The '99 date code on the outside puts it outside the time period (70's & 80's) where SMT was uncommon and hybrid modules were used strictly for their physical compactness (...unless it's a very long-lifetime design, or was for a mid-90's design at a place where their processes changed very slowly). The only other reasons to make this into a hybrid module are for environmental robustness (aerospace or military applications), or to use the laser-trimming process to achieve high initial accuracy on the resistor values. These days you can buy SMT thin-film resistors in 0.1% tolerances off-the-shelf for reasonably cheap, but wasn't always the case. Filters are one place where component precision matters a lot, although the ceramic caps are going to have 1% tolerances at best. It's possible that the resistors were trimmed in production to make up for the tolerances of the caps - if you look at the corner-frequency and Q formulas for the Sallen-Key filter topology (https://en.wikipedia.org/wiki/Sallen%E2%80%93Key_topology#Application:_low-pass_filter), you can see that changes to the capacitor values in both cases can be balanced out by resistor changes that leave the other parameter intact.
Anyways, the short version is that I have no idea about the background of this module! Let me know if you know anything about it.
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Teledyne relays. Really expensive stuff.
Many moons ago I worked for aa board assembly contractor. Among the myriad of boards, there was one small board for a US Navy project. It consisted of a few SN54xx TTL devices, a handful of passive components and a metal-can Teledyne relay.
The relay was only installed after the fully assembled board, minus relay, had successfully passed all the electrical and functional tests. This to prevent scrapping the expensive relay if the board had failed, as we weren’t allowed any repairs on the unit.
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Wow that's wild, that's the level of care I'd expect for a 1000-pin experimental ASIC, not a relay (even a really nice one). I've got a couple boards with their mechanical relays in metal cans, will have to try now (carefully) removing the metal can to take a look at the mechanism.
Meanwhile, I got access to a pretty nice microscope, so here's some close-ups of dies from that Analog Devices HTS-0010SD Track and Hold.
You can see the variety of structures of the resistor arrays; most of them have marks from laser-trimming of the resistances. The arrangement of a lot of them is with many parallel tracks of varying size (effectively a lot of large resistors in parallel), some of which are selectively cut.
(https://live.staticflickr.com/65535/54253623355_e4e241654d_z.jpg) (https://flic.kr/p/2qEd14e)(https://live.staticflickr.com/65535/54253429873_ab82e16e59_z.jpg) (https://flic.kr/p/2qEc1xk)
(https://live.staticflickr.com/65535/54252304152_9214404b4f_z.jpg) (https://flic.kr/p/2qE6eUm)(https://live.staticflickr.com/65535/54253442064_a82ff37dac_z.jpg) (https://flic.kr/p/2qEc5aw)
(https://live.staticflickr.com/65535/54252304147_f8687427e4_z.jpg) (https://flic.kr/p/2qE6eUg)(https://live.staticflickr.com/65535/54253201401_491439ce8c_z.jpg) (https://flic.kr/p/2qEaQCa)
(https://live.staticflickr.com/65535/54390437174_3d775ccd96_z.jpg) (https://flic.kr/p/2qSid3b)(https://live.staticflickr.com/65535/54390248426_a027fb8dfe_z.jpg) (https://flic.kr/p/2qSheVU)
(https://live.staticflickr.com/65535/54390477318_0667b6c94b_z.jpg) (https://flic.kr/p/2qSipYj)(https://live.staticflickr.com/65535/54390477298_5da88c3792_z.jpg) (https://flic.kr/p/2qSipXY)
Then we have the transistor array (only 2 of which are used):
(https://live.staticflickr.com/65535/54253429833_36526e5cd9_z.jpg) (https://flic.kr/p/2qEc1wD)
...a discrete transistor:
(https://live.staticflickr.com/65535/54253623375_49185f5c7a_z.jpg) (https://flic.kr/p/2qEd14z)
...and what I think is the dual JFET, if I remember correctly:
(https://live.staticflickr.com/65535/54253623390_13fbdf283e_z.jpg) (https://flic.kr/p/2qEd14Q)
Edit: updated with better photos, now that the microscope's light source is fixed
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TRT 3511.150.1351
Hello D. Straney,
Module might come from manufacturer 'TRT Defense', subsidiary of Philips.
Location : 'Moncel les Luneville' and/or 'Lunéville', France Departement (means county/region) n°54 : 'Meurthe et Moselle'
It was later (1990 ?) bought by Thomson-CSF (now Thales) so the name was changed to 'Thomson TRT Defense' (TTD)
TRT means 'Télécommunications Radioélectriques et Téléphoniques'
Plainly military stuff : the module might be an IF or audio filter for some kind of radio receiver or radar analog processing.
Information is really sparce on the Internet
https://www.aicprat.fr/news/la-belle-histoire-de-thales-saison-4-episode-03-12238 (https://www.aicprat.fr/news/la-belle-histoire-de-thales-saison-4-episode-03-12238)
https://copainsdavant.linternaute.com/e/t-r-t-defense-1578696 (https://copainsdavant.linternaute.com/e/t-r-t-defense-1578696)
https://copainsdavant.linternaute.com/e/thomson-trt-defense-194688 (https://copainsdavant.linternaute.com/e/thomson-trt-defense-194688) (most recent date is 1997)
https://www.senat.fr/questions/base/1990/qSEQ900710730.html (https://www.senat.fr/questions/base/1990/qSEQ900710730.html) (Q/A to MP)
https://questions.assemblee-nationale.fr/q9/9-57726QE.htm (https://questions.assemblee-nationale.fr/q9/9-57726QE.htm) (Q/A to MP)
Copy the URLs here (https://translate.google.fr/?hl=fr&sl=auto&tl=fr&op=translate) for english translation.
No information found that is more recent than 1997.
No documentation about TRT electronic parts or modules found.
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Appreciate the background. It is really hard to find information about them online!
Here's another from the same manufacturer:
TRT 3511.150.13441
(https://live.staticflickr.com/65535/53495672032_9c5ee2ba84_z.jpg) (https://flic.kr/p/2pveiwY)
(https://live.staticflickr.com/65535/53496983115_941bbc75b5_z.jpg) (https://flic.kr/p/2pvm2gR)
This one's very simple inside: 4 sets of diodes with their cathodes connected to capacitors, and the capacitors referenced to a common circuit ground(?). There's also a completely isolated diode (on the right). One diode-and-capacitor section (2nd from left) has 2 diodes connected in parallel.
I'm stumped about the use case for this module. The diode-into-capacitor connection suggests to me either "analog peak detector", or "power supply output" (such as the output-side diode and capacitor for a multi-output flyback converter). The thick traces and very large-die-size diodes support the "power" theory, while the lack of surrounding precision circuitry (op-amps, etc.) that you'd want for good peak detection, overall says that it's likely part of a power circuit.
However, I don't think these are the output rectifiers for a multi-output power supply. In the case of a switch-mode power supply, with 100 kHz+ switching and significant harmonic content in the Mhz range, the layout geometry doesn't make sense: long, winding ground trace provides a terrible high-inductance connection and makes those capacitors halfway-useless. In the case of an aircraft-power 400 Hz power supply (the output of a step-down transformer, for example), the capacitors are too small to be useful in a frequency range where the layout doesn't hurt it - I measured 86-92 nF across the capacitors, so they're probably 100 nF nominal. Overall, the capacitors probably can't being relied on for any kind of significant power supply filtering: at "low" frequency they'd be useless because of low capacitance, and at "high" frequency they'd be useless because of large layout inductance.
The only situation that makes sense to me, then, is a low-frequency power application not involving ifltering. The only thing I can think of is something like a snubber for inductive loads (valves, solenoids, large relay coils, etc.): these diodes could be serving as the anti-parallel diodes that "catch" and redirect the stored "flyback" energy when an inductive load is switched off. In the end, though, I really have no idea. Let me know if you have any thoughts.
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Hello D. Straney,
Appreciate the background. It is really hard to find information about them online!
Here's another from the same manufacturer:
TRT 3511.150.13441
IMO, it is a deliberate choice that we can't find any documentation about these modules on the Internet.
This is only for military purpose. And these people do not talk or publish anything about their former or current work. I guess similar guidelines apply in the USA.
IMO, it is rather a wise decision and it has to be like that.
Indeed, this 'TRT 3511.150.13441' module looks rather basic. All of the use cases you suggested are plausible.
I have no clues why they put such a simple circuit inside an hybrid module.
Reliability purpose ? Security reasons to hinder retro-engineering and/or duplication ?
Is it just a wired programming or parameter defintion module, that activates dedicated features on a host system ?
Was that module intended to update or correct a failed design on an existing board or sub-assembly ? So it might be a replacement part for a formerly designed module.
Did you measure the forward voltage of the diodes (and perhaps their reverse leakage current) ?
I also found that TRT settled at two other locations : Guyancourt (dept. 78, Yvelines) and 'Brive-la-Gaillarde' (dept. 19 Corrèze).
And their realm is clearly military optronics.
Thermal cam for combat tank (http://militaryphotoreport.blogspot.com/2014/10/amx-30-b2-forad.html)
Tunable laser source (https://jp4.journaldephysique.org/articles/jp4/abs/1994/04/jp4199404C4143/jp4199404C4143.html)
They were also involved in the multirole combat aircraft 'Dassault Rafale' prototype (https://omnirole-rafale.com/rafale-m02/) at the end of the 80' and early 90', for the frontside optical thread detection and recognition system (*).
If you're looking for more information about these module, consider asking Michel (https://www.youtube.fr/@lelabodemichel5162) : he often dismantles military gear. As far as I know, he speaks a little bit english.
(*) called 'Optonique Secteur Frontal (OSF), with staggering requirements, as written in 1989 : 40 NM range for (passive) thread detection and target follow-up.
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I agree that missing info on the module is unsurprising. I was just surprised that it's hard to find even information on the company itself :) So I appreciate the background info you've found on them, that's interesting.
The "hybridization" of this module could be for a combination of diode heatsinking, and reducing the number of solder joints (I believe MIL-HBK-whatever reliability measures rated wire bonds as significantly more reliable than solder joints? Less physical mass for vibration susceptibility, more flexibility for thermal cycling). Military optical systems seems like a rough environment, as that's all things that have to be mounted to the outside of vehicles. It's also possible they were making a highly-module-enclosed system anyways and so it was little effort to just make one more hybrid.
Good question on the diode ratings: took a quick forward voltage reading and I think they're likely Schottkys. I don't know the test current that my Fluke uses in "diode check mode", but these measured ~0.4V, while other 1A junction rectifiers (1N4001-ish) measured 0.6-0.7V and some 1-3A power Schottkys I have measured more like 0.2V.
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Yet another TRT hybrid:
TRT 3511.181.28601
(https://live.staticflickr.com/65535/53496987985_8e3648403a_z.jpg) (https://flic.kr/p/2pvm3HP)
Inside, this one's more complicated, as the traces have to cross over each other in a few places. The blue you can see is an insulating layer placed in between stacked conductive layers, and underneath wirebonds that cross traces. I had to probe around a bit on this one to trace out the circuitry, doing continuity checks with needles.
(https://live.staticflickr.com/65535/53496866564_6a34de80b4_z.jpg) (https://flic.kr/p/2pvkqCm)
There's two TL082 dual JFET-input op-amps:
(https://live.staticflickr.com/65535/54296953341_8547fa3cd5_z.jpg) (https://flic.kr/p/2qJ35xX)
...and an LM101 single externally-compensated op-amp:
(https://live.staticflickr.com/65535/54296075477_a886b78fe4_z.jpg) (https://flic.kr/p/2qHXzAn)
Let's look at the schematic:
[attachimg=1]
Some parts of it make sense, for example...
The Inverting Input Stage in the middle is a standard inverting amplifier.
The Active DC Removal is an integrator whose output is mixed with an input signal (via R15 & R16), which has the effect of cancelling any DC that appears at the R15/R16 junction. The advantage over just using an RC HPF is, I think, that you can choose your R & C however you want, and still maintain fairly low output impedance for a large time constant, without having to use a massive capacitor value.
Pins 22 & 4 seem to allow selecting an additional capacitor to put in parallel, to increase the time constant more (allow lower-frequency signals).
Separately, up above, there's an Envelope Detector consisting of C2, D4, D3, and C1. This works like the charge pump circuits used for generating double or negative-voltage power supplies, but here is used on a signal instead; C1 is charged up to (roughly) the peak-to-peak amplitude of the input signal from U2A, minus two diode forward voltages.
This envelope amplitude is filtered by a "fast rise / slow decay" filter (R3, R2, D2, C7), and compared against a fixed threshold by U3. Strangely, the LM101 op-amp is used as a comparator here - I don't know why, when perfectly good dedicated comparators are available, and they even go as far as adding an external compensation capacitor. I triple-checked the connections to make sure I didn't have the two inputs reversed, but no.
There's also a strange little peak detector circuit (R4, C3, etc.) which feeds the envelope signal through its own RC time constant, with a diode that may lead to an external peak-detector capacitor. A control signal can turn on a JFET that discharges/resets this external peak-detector cap.
The part I really cannot figure out is the section at the bottom-right, marked as ?????. The signal which has already had its DC component removed by U1A is for some reason fed through another series cap (C9), and into a strange circuit which again uses an op-amp (U2B) as a comparator. R10 & R11 add a small positive offset to In-, while In+ sees the input signal with a floating voltage added to it. This floating voltage addition is created by tantalum capacitor C8 (the orange one in the internal photo above).
First of all, comparing an input signal against itself plus a variable offset seems strange, as that feels like the input signal itself is irrelevant. How does C8's voltage get changed?
- Pin 7 & Q2 can discharge C8, to reset it to ~0V
- When Q3 is on (envelope detector is below threshold), C8 is slowly discharged through R14
- When Q3 is off (envelope detector is above threshold), C8 is quickly charged through R13 & D8
This feels kind of like a timing ramp, based on the detected envelope of a reflected radar or optical pulse, but done in a primitive way with very slow-reacting (µs-scale) parts - so definitely not meant for anything high-speed. I also don't understand where the current is supposed to flow when C8 is charging through R13 & D8: there's no DC path (except to Vcc) on the negative side of C8, so this current would just charge C9's voltage higher and higher.
There's also some kind of diode-bridge possible limiter circuit up in the top-left corner. It's completely unconnected to the rest of the circuit, except for the power rails. The limiter action comes from the fact that output current sourcing & sinking happens only through R22 & R21, not from the input signal directly. So by putting a load resistance to gnd on the output (let's suppose that's what the 40Ω R20 is for), the voltage dividers formed by R22/R20 & R21/R20 would set the maximum positive and negative voltages that it can output. At higher or lower input voltages, the input diodes then simply turn off.
Anyways, to sum up, I have no idea what this is doing, beyond some kind of signal detection. Let me know if you have any ideas. There's one more TRT hybrid to go, so hopefully that one will have a more obvious function once I trace its circuitry.
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Ok, turns out I missed something important in that mystery circuit: there was actually a hidden ground connection on one side of C9. So now it makes a lot more sense:
[attachimg=1]
The Active DC Removal circuit with the U1A integrator is its own independent circuit section, that doesn't interact with the rest of the circuitry directly.
The former-mystery circuit is now shown to be a Timer. U2B compares C8's voltage against a fixed reference (created by R10 & R11). C8 charges when the envelope detector sees a signal above the threshold, and Q3 is off. C8 discharges slowly (maybe barely at all?) when the envelope detector doesn't see a sufficiently large signal. C8 is reset when an external pulse on pin 7 turns on Q2 and discharges C8 completely.
Overall, the output of U2B (pin 6) seems to go high when an input signal has been present (to the envelope detector) for a certain amount of time, and C8 is allowed to charge past the R10/R11 threshold.
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Wow, nice pics! :-+
Thank you. Subscribed.
I find the accompanying schematics very interesting, made me want to experiment with certain ideas seen there. :-DMM
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'VOIE CONTR' probably means 'VOIE de CONTRôle'
in english : control path, control circuit, control side-chain
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Sampling bridge
This is a standard 4-diode sampling bridge: I can't find any references that explain their basic operation well, but the idea is that you forward-bias all the diodes (with a current source) to turn them all on.
Some explanations are in the Tektronix' concepts series https://www.davmar.org/concepts.html (https://www.davmar.org/concepts.html) at page 66 of 254 here: https://www.davmar.org/TE/TekConcepts/TekSamplingCircuits.pdf (https://www.davmar.org/TE/TekConcepts/TekSamplingCircuits.pdf) not sure if that is well enough.
Another way at looking at it might be from the perspective of translinear circuits, as in this video at minute 13:20
Bipolar Translinear Circuits, lecture by Barrie Gilbert
Computer History Museum
https://www.youtube.com/watch?v=LQNJVtcFrCc&t=805 (https://www.youtube.com/watch?v=LQNJVtcFrCc&t=805)
Thought it was interesting that they advertised the 5 ps jitter in the sample window timing, but the slow settling time and long sampling window needed make that less impressive in practice than it sounds - unless you're going for serious precision on a slower signal, like if building a precision multi-Mhz LVDT for some reason.
My guess is the 5ps spec was useful in case somebody wants to make a sampling head, or a sampling oscilloscope like in the pdf above, where the ADC is much slower than the input signal, yet it is still possible to observe the much faster input signal because the signal is repetitive, and at each trigger only one sample is taken, but each time the sample is taken slightly later relative to the trigger moment.
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Some explanations are in the Tektronix' concepts series https://www.davmar.org/concepts.html (https://www.davmar.org/concepts.html) at page 66 of 254 here: https://www.davmar.org/TE/TekConcepts/TekSamplingCircuits.pdf (https://www.davmar.org/TE/TekConcepts/TekSamplingCircuits.pdf) not sure if that is well enough.
Perfect, thanks, added it to the post: didn't want to derail the circuit explanation by having to describe sampling bridge operation from scratch (badly) by myself.
My guess is the 5ps spec was useful in case somebody wants to make a sampling head, or a sampling oscilloscope like in the pdf above, where the ADC is much slower than the input signal, yet it is still possible to observe the much faster input signal because the signal is repetitive, and at each trigger only one sample is taken, but each time the sample is taken slightly later relative to the trigger moment.
That's what I would've thought for a mismatch in small-signal bandwidth & jitter, but the sampling window seems weirdly long for that, given the high small-signal bandwidth & low jitter. With the 14 ns sampling window needed for 0.1% settling, the jitter is 1/3000th of the sampling window time - good for precision but also unnecessary because the errors from harmonic distortion, switching transient, imperfect feedthrough rejection, etc. are all much larger than that. I'm guessing they didn't design it specifically for low jitter as the "limiting factor", but it just ended up being much lower than needed :) (and therefore good as a marketing point)
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Ok, here's the final TRT hybrid I have:
TRT 3511.181.28681
(https://live.staticflickr.com/65535/53496989540_4e7df9cdf3_z.jpg) (https://flic.kr/p/2pvm4bC)
It has "G.D.S." on the lid (don't know what that stands for) and dates from 1994.
It's not that different from the previous 3511...28601 inside in general:
(https://live.staticflickr.com/65535/53496868149_ca48df4b5a_z.jpg) (https://flic.kr/p/2pvkr6F)
(https://live.staticflickr.com/65535/53496567706_704617e6dc_z.jpg) (https://flic.kr/p/2pviTMC)
There's a dual JFET-input op-amp that isn't marked, but looks similar to the Zeptobars photo of the ST TL072 (https://zeptobars.com/en/read/ST-TL072-JFET-dual-opamp):
(https://live.staticflickr.com/65535/54296078992_c90d7d30a0_z.jpg) (https://flic.kr/p/2qHXACY)
Like the previous TRT hybrid, it also has an LM101 op-amp:
(https://live.staticflickr.com/65535/54297382780_4d9eb6efaf_z.jpg) (https://flic.kr/p/2qJ5hd5)
Let's look at the schematic I traced out:
[attachimg=1]
The top section, the non-inverting gain stage, is pretty straightforward. There's one of the JFET-input op-amps set up for non-inverting gain (set by R2 & R3), referred to a negative offset voltage created by R4 & R5. A series resistor on the output, and a separate transistor which can selectively shunt the output signal to ground, implements some sort of "output blanking".
The bottom section starts off with an integrator based on U2, which integrates a signal coming in on pin 21. It seems somewhat flexible; shorting pins 23 & 24 together adds an extra capacitor in parallel (slowing down the response), and there's a pin directly to the virtual ground (pin 22) that could be used for a different-value input resistor.
Anyways, the integrator is apparently only supposed to work with positive outputs: D1 across the feedback path ensures that the output can't go more than ~0.7V negative. (If it "tries" to, then D1 turns on and turns U2 into a buffer with a grounded input) So, the input could be positive or negative, but the integrator's output can only go positive. C5 is a compensation capacitor which adds a Miller capacitance across the LM101's internal gain stage (see the LM101 datasheet for an internal schematic and details (https://www.ti.com/lit/ds/symlink/lm101a-n.pdf)), but there's also C4 - by connecting the inverting input to the output of the internal differential-to-single-ended converter, this seems to actually add some positive feedback, if I'm interpreting the internal schematic correctly.
After the integrator is a comparator, using the 2nd half of the JFET-input op-amp: this sums a reference voltage with the integrator output, and compares the result with 0V. The reference voltage is not at all precise; it's created with a zener diode from Vcc, and a much larger resistor from negative supply Vee. I think the only way this makes sense is that when the integrator's output is 0V, U1B's input is biased negative.
What I think happens here, is that the input signal gets integrated, and when the integrated input is large enough (positive), the comparator's output goes high. This allows JFETs Q1 & Q2 to turn on, and short the integrating capacitor, therefore resetting the integrator. This drops the integrator's output back to 0V and so the comparator's output goes low again, and the process restarts. The brief time during which U1B's output goes high creates an output pulse in two different formats:
The pulse output circuitry level-shifts the Vee-to-Vcc bipolar U1B up to ~0V to 2*Vcc.
The open-collector output pulses Q3 on.
This lower part of the schematic, then, seems like a voltage-to-frequency converter. A larger (more negative) input voltage means that the integrator's output reaches the comparator threshold faster, to generate a pulse and reset the integrator, therefore creating a shorter period & higher frequency. There's yet another auxiliary output, between D2 & Q5, which activates a (presumably negative) open-collector output to pull it up to 0V, when the integrator output is below 0V (D2 somewhat cancels the Vbe of Q5). This feels like maybe some sort of anti-latchup feature or "wrong input polarity" output, but not sure.
Let me know if you have any circuit insights.
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Speaking of voltage-to-frequency (V-F) conversion, here's the...
Teledyne/Philbrick 4735 Voltage-to-Frequency Converter
The TRT V-F circuit was perfectly fine for its purpose (whatever that was), but was a rough implementation with lots of sources of error: the time required to discharge the integrator cap, the finite on-state resistance of the JFETs giving an imperfect reset, the large delays of op-amps used as comparators, the reference voltage derived from the imprecise supply voltage, etc. Let's explore the other end, instead, of high-precision V-F converters. The datasheet for this part lists some impressive specs: a 126 dB dynamic range (±10 µV to ±10V input), <50 ppm/K temperature sensitivity, and 50 ppm non-linearity (relative to full-scale)...up to 1 Mhz.
(https://live.staticflickr.com/65535/53372970967_ec45b73eb4_z.jpg) (https://flic.kr/p/2pjoqMn)
There's enough traces running underneath each other and underneath the ceramic resistor-network sub-subtrate where I can't follow them visually, that tracing the circuit here would be a sanity-stretching exercise. Instead, I want to talk about the general theory of operation and the principles behind similar precision V-F converters.
First, some more photos of the inside, though:
(https://live.staticflickr.com/65535/53373882721_512542e02d_z.jpg) (https://flic.kr/p/2pjt6Pg)
(https://live.staticflickr.com/65535/53770187804_f0a3aaa461_z.jpg) (https://flic.kr/p/2pVugvw)
(https://live.staticflickr.com/65535/53834979964_f8fab9868f_z.jpg) (https://flic.kr/p/2q2dkXJ)
(https://live.staticflickr.com/65535/53770279280_0d7e58368b_z.jpg) (https://flic.kr/p/2pVuJGG)
If you look closely, you can see that the silicon dies consist of a lot of discrete diodes and transistors, plus 3 ICs. These ICs are an LM101 op-amp:
(https://live.staticflickr.com/65535/54296951956_89de6b5637_z.jpg) (https://flic.kr/p/2qJ3595)
...a PMI OP-02 op-amp:
(https://live.staticflickr.com/65535/54297377810_163de67fb8_z.jpg) (https://flic.kr/p/2qJ5fJo)
...and a 54C04 hex logic inverter (the military-grade, CMOS version of the 7404):
(https://live.staticflickr.com/65535/54296952041_154aa56097_z.jpg) (https://flic.kr/p/2qJ35ax)
The presence of these "general-purpose building block" ICs doesn't tell us anything about how it works, so first stop is the datasheet:
[attachimg=1]
The 4731/4733/4735 V-to-F is a free running (astable) voltage controlled multivibrator. See Figure 4. The effective currents from the four inputs (A, B, C, & D) are summed at the minus input of op amp A1. A1 and transistor Q1 form a precision current pump, producing current I from the collector of Q1, which is a linear function of the A1 input currents. Current I charges capacitor C at a rate which is a precise linear function of the V-to-F's input signal.
When the voltage impressed on C (due to I) reaches a fixed precision threshold, the Schmitt-Trigger output changes state and triggers the one-shot (monostable) multivibrator, which in turn produces a constant width output pulse. This pulse performs two functions. Amplified by Q2, it is the output of the V-to-F and functionally activates the Precision Charge Dispenser (PCD). The PCD discharges C to the same "zero" level every time an output pulse is produced. Thus, capacitor C is repeatedly charged between two precise voltages at a rate which is a linear function of the V-to-F input signal, producing the waveforms shown in the timing diagram, Figure 7. That is, the rate of charging C, (the repetition rate of charging C and thus the output frequency) are functions of the V-to-F voltage and/or current inputs.
So you can see that the overall principles aren't actually too different than the comparatively-rough V-F in the TRT hybrid before. Convert input voltage to a current, use that current to charge a capacitor, and then somehow reset that capacitor when its voltage reaches a threshold. The difficult parts are in how these steps are performed though. It doesn't say anything about how the PCD (Precision Charge Dispenser) works, as that's most of the Special Sauce(tm) right there. For comparison, though, let's look at some Bob Pease notes on V-Fs.
LM131
Here's a schematic from National Semiconductor (now Texas Instruments) application note AN-D, showing the internal workings of the LM131 V-F IC:
[attachimg=2]
Rather than trying to reset the capacitor each cycle to a fixed voltage level, instead it removes a fixed amount of charge each cycle, which as the application note explains:
Generally speaking, the circuit is a feedback loop that keeps this capacitor charged to a voltage very slightly higher than the input voltage, VIN. If VIN is high, CL discharges relatively quickly through RL, and the circuit generates a high frequency. If VIN is low, CL discharges slowly, and the converter puts out a low frequency.
Philbrick 4701
One of the difficulties of this approach is the method of removing (adding?) charge to the timing capacitor, with a precision current source gated by a precision timer. Because the total charge removed is current * time, imprecisions in either the current source or the one-shot timer will feed into the output, and if you're trying to achieve a very temperature-stable V-F, this adds a lot of sources of drift to worry about. (I believe these were popular for telemetry, for industrial processes and aerospace stuff, so you can imagine the environmental requirements of both of those) In one of his columns, "What's all this V-F converter stuff, anyhow? (Part II)", Bob Pease describes the circuit he came up with for the Philbrick 4701 V-F.
[attachimg=3]
There's a lot happening there, but the key part to know is that the "precision charge dispensing" here is done by clamping the comparator's output voltage to a precise level, and then feeding back the pulse output to the timing capacitor via another capacitor. If you put two capacitors in series and place a voltage across them, the new charge that ends up in the "bottom" capacitor only depends on the capacitance ratio and the voltage, independent of time (as long as there's enough time for everything to settle). So, there's no precision timing to be done here - as long as the feedback capacitor value is stable, and the output voltage clamp is stable, then the charge added to the timing capacitor at every output pulse will be stable.
The bipolar output voltage clamping is done by a diode bridge (D4-7) with a zener (D10) in the middle; the forward voltages of the diodes are cancelled elsewhere by D1 & D2 (D3 & Q1 provide a "virtual ground" at Vf(D1)+Vf(D2) to bias one side of C2). The feedback capacitor is C2, and it's "one of the best capacitors in the house" according to the article. There's some temperature coefficient cancellation going on, where C2's tempco gets cancelled by the difference between D4-7 and D1-2's tempcos (they're run at different currents), but that's a whole separate subject.
There's more examples to point to by Jim Williams and Stephen Woodward, but hopefully you get the idea at this point: current input feeds a capacitor connected to a comparator, with a charge pump wrapped around it. Hope this was interesting.
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Post #8 has some beautiful photos.
What camera setup did you use?
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Thanks! The one with the resistor arrays? (https://www.eevblog.com/forum/projects/de-capping-circuit-analysis-of-hybrid-modules/msg5785853/#msg5785853 (https://www.eevblog.com/forum/projects/de-capping-circuit-analysis-of-hybrid-modules/msg5785853/#msg5785853)) Can definitely see a jump in the microscope image quality in this thread ;D Last month I found out there's a very old but very nice metallurgical microscope in the basement of the lab where I study - had to replace the eyepieces, get a new xenon bulb, and clean the objective lenses, but that's what I've been using for the high-quality microscope shots. It's an Olympus BX51M, which includes a nice bright coaxial light source, hence the good illumination - for the camera I've been using a 2MP Celestron camera (https://www.celestron.com/products/2mp-digital-microscope-imager) (got for free from another lab shutting down) that basically replaces an eyepiece.
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For something very different, let's look at an all-digital part:
LMT.RP H442 clock divider
I don't know where this came from; I got it in the same batch as the TRT modules above.
(https://live.staticflickr.com/65535/53496981595_bed97fd1a7_z.jpg) (https://flic.kr/p/2pvm1PD)
(https://live.staticflickr.com/65535/53495670382_4644716d52_z.jpg) (https://flic.kr/p/2pvei3w)
You can already see a distinct lack of passives, which hints at it being full of digital logic.
The 4 dies in the middle are all 74LS107 dual J-K flip-flops. The "107A" is written on the metal layer, while there's "73A" written in the silicon doping, which makes me suspect that the 74LS73 (also a dual J-K flip-flop) uses the same design except for a different metal layer. The pinout of these parts is not symmetric, and you can see that the layout reflects that: things look symmetric around the horizontal center-line, but as you get further outwards towards the top and bottom, the symmetry disappears quickly.
(https://live.staticflickr.com/65535/54317534829_7ce0c2ba0c_z.jpg) (https://flic.kr/p/2qKRyHc)
There's a single 74S74 dual D-type flop-flop in the bottom-left corner:
(https://live.staticflickr.com/65535/54316413897_5e1a0338df_z.jpg) (https://flic.kr/p/2qKKPuM)
The remaining 2 smaller dies are 74LS00 quad NAND gates. These end up being severely under-used; only 1 gate is used from one die, and 2 from the other die. I like how compact the layout is here, to the point that they put the part number markings in between the bond pads.
(https://live.staticflickr.com/65535/54316414372_27d999111e_z.jpg) (https://flic.kr/p/2qKKPCY)
The internal connections were easy to trace...but making sense of it was much harder! Here's the schematic:
[attachimg=3]
Divide-by-2: produces Clk1
It starts pretty simple at the top: a clock enters, gets inverted (presumably for phase purposes?) and divided by 2, by the 74S74. Not much to see here. This divided-by-2 clock is then used in the middle section.
Divide-by-5: produces Clk3
Let's skip to the bottom section, because that's the next-simplest. This section takes its clock from the middle section that we skipped. The way that J-K flip-flops work is that on each clock cycle, complementary J & K inputs force it to a specific state (J=1, K=0 → 1, J=0, K=1 → 0), while both inputs low makes no changes to the state, and both inputs high toggles the state. So the connections between U1A→U2B, and U2B→U1B, where the previous flip-flop's Q & !Q are connected to the next flip-flop's J & K, essentially copy the previous flip-flop's state. The connection of U1B→U1A is a little weirder because it uses U1A's asynchronous reset to force U1A low as soon as U1B's output goes high. If I'm interpreting correctly, this creates a divide-by-5 effect, looking at the states after each clock falling edge:
[attachimg=1]
Divide-by-N/N+1
Saving the most complicated for last, take a look at the middle section. How this behaves is controlled by an external input, pin 14.
When pin 14 is low, everything's reasonably simple: U6A's output is always high, so U6D's output is always low, and U3B never gets to toggle (J & K are always low). If we start from an all-zeros state, U3B is continuously forced low through its async reset by U3A's output being low, so this holds U4A & U4B low through their reset pins, so U3A never gets a chance to go high and "break the loop" here. This means that all that happens is U2A has both J & K held high (due to being connected to U3A's !Q), so U2A just sits there happily toggling its output, producing a divide-by-2 output on Clk2 to feed the bottom section (the divide-by-5).
When pin 14 goes high, though, things get weird. Mapping out the states makes it much easier to understand what's happening:
[attachimg=2]
Now, U3B is allowed to toggle sometimes because its J & K inputs are high whenever Clk3 (the divide-by-5 output) is high. But Clk3 is a divided-by-5 version of Clk2! So what happens here, is that it goes back and forth between states 1 & 2 for 10x Clk2 cycles (5x Clk3 cycles). When Clk3 goes through a full cycle, it produces a falling edge on U3B's clock pin, which toggles U3B to a "high" state. Now, U4A & U4B are no longer being forced low by U3B. This allows it to progress through states #3-5, which produce 1x Clk2 pulse over 3 states. After this last state, it ends up at all-zeros again, and so the whole cycle restarts.
The effect this has, is that when pin 14 is high, the middle section produces 6 output cycles (on Clk3) over 13 input cycles (on Clk2): the 10 cycles to wait for a Clk3 falling edge, plus 3 extra cycles for states #3-5. Therefore, pin 14 switches the division ratio of this middle section between 2 and 13/6.
Purpose
When you look at the number "2" as 12/6, then the middle section makes more sense: it can either divide by 12/6, or 13/6. This very much puts me in mind of a fractional-N frequency synthesizer's divide-by-N/divide-by-N+1 switching (https://en.wikipedia.org/wiki/Frequency_divider#Fractional-N_synthesis), just like in the SINCGARS military radio's frequency synthesizer I looked at before (https://www.eevblog.com/forum/projects/reverse-engineering-some-old-sincgars-military-radio-boards/msg5231052/#msg5231052). The overall division ratio is switchable between 2*12/6*5 = 20, or 2*13/6*5 = 21+2/3.
I believe this module was used in a frequency synthesizer, either for a radio, or some other kind of RF equipment (jamming, surveillance, etc.). It was made in 1997 according to the date code on top, and I'm pretty sure there were commercial self-contained frequency synthesizers at a much higher level of integration by then - but judging by the fact that it was constructed as a hermetic hybrid, it's (1) probably some kind of aerospace or military application, and (2) may have been designed significantly earlier than that: see point #1 again. Considering the maximum frequency of "74LS" logic, this can't have been dealing with any particularly high frequencies, probably 10 Mhz at most.
Anyways, there you have it, that's how to make your fractional-N-synthesizer's frequency divider out of discrete logic. Given how much convoluted logic is involved with these flip-flop states, I can only imagine the poor engineer who had to twist their brain into knots to come up with this.
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For something very different, let's look at an all-digital part:
LMT.RP H442 clock divider
I don't know where this came from; I got it in the same batch as the TRT modules above.
Perhaps a clue here (https://fr.wikipedia.org/wiki/Le_Mat%C3%A9riel_t%C3%A9l%C3%A9phonique).
Headquaters in Boulogne-Billancourt (https://francearchives.gouv.fr/fr/facomponent/816ed0c45b0bfa4f0bff13a90051f5d55567f857) (departement 92, Hauts-de-Seine), France
This module might have been used in a PABX.
'.RP' : That's a bit surprising. At first sight, I'd thing about the name or acronym of a subsidiary or internal division.
But 'RP' is also a today much used acronym which means 'Région Parisienne' = Paris + its suburb.
Maybe it's just a coincidence.
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Oh that's interesting, glad you recognized "LMT" as a company name. In that case, it makes me wonder if the TRT hybrids were also from large-scale-communications (phone, etc.) applications? That document on TRT's background (interesting read by the way, thanks!) mentioned their thermal imaging business, but haven't seen anything about whether or not they had non-military projects: the "telephone, radio, & telegraph" name at least suggests communications as well.
If all these TRT & LMT hybrids were from phone exchanges or other utility-scale telecom applications, maybe acquired in a single surplus batch by the distributor that sold them to me, that would explain a lot of the design choices too. Telecom equipment would be less sensitive to environment (unless it's sitting up on a cell or radio tower!) but would have similar long-life & reliability requirements, and a similarly conservative design philosophy.
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That's all for my Polish batch of French hybrids (thanks to timeandfrequency for providing background on those); now here's something a little more standard.
Burr-Brown ADC84KG 12-bit ADC
(https://live.staticflickr.com/65535/54086395184_2b3b47dd98_c.jpg) (https://flic.kr/p/2qpqUWU)
There's a few dies in here, but it's hard to tell how they're connected with multiple wiring layers buried in ceramic. It's mostly made up of a few ICs though, so let's see if we can figure out how it works by looking at those...
The big rectangular one looks like a DAC:
(https://live.staticflickr.com/65535/54329521754_9d8600a1fe_c.jpg) (https://flic.kr/p/2qLV11j)
Notice the row of 12 dark-pink resistors near the top-right corner - these have laser-trimming marks (in green). There's another smaller resistor array arranged as a column with 6 rows, near the bottom-center, plus a chunk of unused circuitry (no metal layer) just to the bottom-left of center - a lot more resistors too. The simplicity of the remaining circuitry (few transistors) and the number of precision resistors, especially in regular arrays, is what strongly suggests to me that this is a DAC. The arrangement doesn't seem quite right for a R-2R ladder (https://en.wikipedia.org/wiki/Resistor_ladder#R%E2%80%932R_resistor_ladder_network_(digital_to_analog_conversion)), but I'm not familiar enough with the details of other integrated-DAC schemes to guess at exactly what it's doing. It's probably some kind of segmented DAC (https://www.analog.com/media/en/training-seminars/tutorials/MT-016.pdf), with multiple resistor ladders to handle different parts of the output range.
Having a DAC makes sense so far, though. The most popular way to create an ADC with more than a few bits is by Successive Approximation (https://en.wikipedia.org/wiki/Successive-approximation_ADC): essentially, you guess a number, convert it to an analog voltage, look at whether it's larger or smaller than your input, and then refine your guess upwards or downwards based on that. The digital logic is a bit complicated, but it can be efficient if you approach it as a binary search (https://en.wikipedia.org/wiki/Binary_search).
The big square die is a digital gate array:
(https://live.staticflickr.com/65535/54329521929_41c3c22c78_c.jpg) (https://flic.kr/p/2qLV14k)
This would be the logic that controls the successive approximation process. You can see that the IC itself is made by AMI (Burr-Brown probably didn't want to bother with non-analog IC processes), and there's some interesting test pads in the top-left corner for characterizing some simple silicon structures.
A successive approximation DAC needs a comparator, however, to compare the input signal against each "guess" in analog form from the DAC. That seems to be the purpose of one of the smaller dies, an LT119 comparator.
(https://live.staticflickr.com/65535/54328396527_a7e9a4b54f_c.jpg) (https://flic.kr/p/2qLPevR)
It has a fast propagation delay (compared to the "jellybean" parts like the LM339, at least) of 80 ns, which makes sense as the ADC is going to make ~12 comparisons for each conversion, so the comparator can easily be a limiting factor in the conversion rate.
The final IC is what looks like a single op-amp, made by PMI (Precision Monolithics Inc.):
(https://live.staticflickr.com/65535/54329523103_f26f82feee_c.jpg) (https://flic.kr/p/2qLV1pz)
I may have developed the op-amp version of pareidolia (https://en.wikipedia.org/wiki/Pareidolia) after looking at a lot of die photos...but the bond pad arrangement does actually match the standard single-op-amp pinout if the big structure on the right-hand side is the input differential pair.
There's lots of potential uses for an op-amp inside an ADC, but if we cheat and look at the ADC84KG's datasheet (https://download.datasheets.com/pdfs/2004/0528/index/cs/txn/qd/d0009623.pdf), it shows an uncommitted op-amp to be used for input buffering - which is probably this IC right here. The block diagram also confirms that it uses successive approximation.
The datasheet also mentions some thin-film trimmed resistor networks, as general-purpose "building blocks" to be used externally if you want to add attenuation or gain to your input signal. These are the 3 small squares with S-shaped patterns in the overview photo above. Here's one of them up-close, so you can see the laser-trimming marks:
(https://live.staticflickr.com/65535/54329521934_cfec848225_c.jpg) (https://flic.kr/p/2qLV14q)
(This is among the least photogenic of the wirebonded resistors that I've seen under the microscope; I've got an album full of more interesting-looking ones (https://www.flickr.com/photos/147639706@N02/albums/72177720323986169/)).
There's also a few discrete semiconductors: a couple diodes, and a transistor. This is the transistor, which is an N-channel MOSFET (Calogic SD211) (http://calogic.net/wp-content/uploads/2019/03//SD211_Datasheet_Rev_B.pdf):
(https://live.staticflickr.com/65535/54329705695_b7473c4eae_c.jpg) (https://flic.kr/p/2qLVWFH)
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Indeed, this 'TRT 3511.150.13441' module looks rather basic. All of the use cases you suggested are plausible.
I have no clues why they put such a simple circuit inside an hybrid module.
Reliability purpose ? Security reasons to hinder retro-engineering and/or duplication ?
You missed one other possible reason: Being able to charge $1,000 each for a bunch of TL072's and some passives.
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The final IC is what looks like a single op-amp, made by PMI (Precision Monolithics Inc.):
I may have developed the op-amp version of pareidolia (https://en.wikipedia.org/wiki/Pareidolia) after looking at a lot of die photos...but the bond pad arrangement does actually match the standard single-op-amp pinout if the big structure on the right-hand side is the input differential pair.
Looks like some "improved LF156", you would have to search PMI databooks for candidates. Offset adjustment on pins 1, 5 and zener trimmed internally. Probably with gate leakage cancellation trick (a dummy JFET whose gate current is mirrored into input pins), I recall that somebody was making JFET opamps like that but I don't remember those type numbers.
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Oh that's an interesting scheme! Yeah I found a databook with rough die photos at bitsavers (http://bitsavers.org/components/pmi/_dataBooks/1986_PMI_Linear_and_Conversion_Products_Data_Book.pdf) but 1986 was the latest they had, and with the 1987 date on the die didn't want to draw any hasty conclusions.
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Indeed, this 'TRT 3511.150.13441' module looks rather basic. All of the use cases you suggested are plausible.
I have no clues why they put such a simple circuit inside an hybrid module.
Reliability purpose ? Security reasons to hinder retro-engineering and/or duplication ?
You missed one other possible reason: Being able to charge $1,000 each for a bunch of TL072's and some passives.
If reliability in a harsh environment is a requirement, then hybrid construction is likely less expensive than printed circuit board construction, especially if you already have the infrastructure to manufacturer hybrids.
Looks like some "improved LF156", you would have to search PMI databooks for candidates. Offset adjustment on pins 1, 5 and zener trimmed internally. Probably with gate leakage cancellation trick (a dummy JFET whose gate current is mirrored into input pins), I recall that somebody was making JFET opamps like that but I don't remember those type numbers.
I have seen old JFET designs which have input bias current compensation. I think it was only used where the JFETs had high input bias current to start with. PMI did it with their OP-15/OP-16/OP-17, which are their improved LF155/LF156/LF157 series. I thought I remembered another example but a quick search did not find it.
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MPC-Woodward HM41200206A Motor Driver
(Thanks to Evilmonkeyz (https://imginn.com/evilmonkeyzdesignz/) for this one)
(https://live.staticflickr.com/65535/53601773302_9c152cb8ef_z.jpg) (https://flic.kr/p/2pEB6Kd)
The thick leads, "BeO" warning on the lid (beryllium oxide, toxic as dust but used for its high thermal conductivity), and the "driver hybrid" label suggest some power handling here. Let's take a look inside:
(https://live.staticflickr.com/65535/53603117045_67ff25e88f_z.jpg) (https://flic.kr/p/2pEHZcc)
There's a lot going on in here, so it's easier to understand with the ICs labeled:
[attachimg=1]
The layout of the 6 power transistors strongly suggests a triple half-bridge used as a 3-phase inverter (https://www.monolithicpower.com/en/learning/mpscholar/power-electronics/dc-ac-converters/three-phase-inverters).
UC1637
(https://live.staticflickr.com/65535/54351912232_8bb81821cf_z.jpg) (https://flic.kr/p/2qNTKV3)
This is similar to the other Unitrode UCx84x-series switch-mode power supply control ICs, in that it provides the building blocks for PWM and a control loop. However, the datasheet specifically lists this as meant for motor control. That makes sense with the 3-phase inverter arrangement of power transistors - I can't see an application where this hybrid would be feeding a 3-phase grid connection, for example, but a motor driver sounds plausible.
Mystery IC
(https://live.staticflickr.com/65535/54344649147_c34306fbe6_z.jpg) (https://flic.kr/p/2qNfwRr)
The UC1637 can only produce 1 PWM signal, but you need 3 phase-shifted PWM signals for driving a 3-phase inverter. This mystery chip seems to provide the "glue" in between the UC1637 and the power transistors, judging by both its contents and external connections.
To translate a single-phase PWM signal into 3x PWM signals, phase-shifted by 120°, requires flip-flops or latches of some kind, to keep track of the current state. This is likely contained in the top & right-hand edges:
[attachimg=2]
To translate each state into the correct combination of 6 outputs, you need some complicated combinational logic. One obvious feature on this chip is two matrices just above the center. It looks like each connection here creates a diode that connects the row to the column, so you'd put your inputs on the rows and get outputs on the columns, or vice versa - a this would be one obvious way to implement the arbitrary state-to-output logic. You can see here that there's two matrices side-by-side, in two stages of logic: it looks like...
- Inputs come into the columns of the right-hand matrix
- Outputs come from the rows of the right-hand matrix, and into the rows of the left-hand matrix
- Outputs come from the columns of the left-hand matrix, and to the gates of the output transistors we'll discuss next
[attachimg=3]
Finally, you can see 6 large power transistors down the left-hand side of the die. These are connected externally to the gate drive circuitry for each power MOSFET, and provide the higher-current output needed to drive the discrete gate drivers:
[attachimg=4]
Mystery quad op-amp
(https://live.staticflickr.com/65535/54345956170_f4507db611_z.jpg) (https://flic.kr/p/2qNneoj)
Based on the layout, I'm pretty sure this is a quad op-amp. Each quadrant has 4 transistors arranged in a square, with the diagonal pairs connected in parallel. This is a scheme used elsewhere on the TL072 (https://zeptobars.com/en/read/ST-TL072-JFET-dual-opamp), TL082 (https://www.flickr.com/photos/147639706@N02/54296953341/), and other op-amps (https://www.flickr.com/photos/147639706@N02/54296078992/) for the input differential pair, to cancel out the effects of thermal gradients across the die that would otherwise produce input offset voltages.
If you look back at the overview above, you can see that this chip is connected (through a few resistors) to the current-sense resistor on the power stage. So at least one of these op-amps is used for amplifying the current sense signal, and producing something that can be worked with. I'm not sure what the other 3 op-amps are used for though - maybe there's multiple gain stages, or averaging to provide an "average current" reading, or some offsets applied, or op-amps used as comparators (don't like doing it in my own designs as there's lots of potential pitfalls, but it's come up in other hybrids I've looked at in this thread!). There's probably an external pin with a current sense signal, that an external computer can use for "motor health" monitoring to read off the current draw.
LM111 comparator
(https://live.staticflickr.com/65535/54344649002_debebdd89d_z.jpg) (https://flic.kr/p/2qNfwNW)
One of the places that the current sense signal likely goes, is to this comparator. The LM111 is pretty fast (165 ns) so I'm guessing this is used for over-current detection and shutdown - if one of the motor windings or connections develops a short to ground, or a power transistor fails "on", then you want to be able to detect that as soon as possible to shut down the system, and avoid making the situation more unsafe by dumping lots of energy as heat.
LM148 quad op-amp
(https://live.staticflickr.com/65535/54344649157_a68a61d8e2_z.jpg) (https://flic.kr/p/2qNfwRB)
Here's another quad op-amp, of a pretty generic variety. I don't know exactly what this is used for; I'd love to trace the exact connections in this hybrid to figure out what all the op-amps are doing, but with multiple layers of traces, it would involve a lot of everything-against-everything continuity checking and be much more trouble than it's worth. This is a pretty generic op-amp, without particularly low offset or bias currents, particularly high bandwidth, etc.
One possible use for the LM148, and some of the mystery op-amps in the quad IC, is as part of the control loop. I don't know for sure that this entire system doesn't run open-loop, but the UC1637 has an error amplifier, and is meant to run closed-loop based on some sort of command signal. The datasheet shows applications circuits both for external speed & position commands, both of which would involve conditioning inputs from external sensors. It's also possible that it runs in a controlled-torque configuration, adjusting PWM based on the measured average current, and then a second control loop (formed out of the external op-amps) controls the torque setting to achieve an externally-commanded speed or position.
Use case
So that's the contents of this module, but where was it used? The "19170" on the lid is a CAGE code that belongs to the "MPC Products" division of Woodward. I hadn't heard of either of these companies before, but if you go back to the 2014 version of mpcproducts.com using The Wayback Machine, it seems that MPC makes electromechanical actuators (rotary and linear motors, gearboxes, etc.) for the aerospace industry including the electronics that drive them:
[attachimg=5]
There's even a section dedicated to hybrid modules, where they show an open hybrid that looks suspiciously similar to this one:
[attachimg=6]
I couldn't find the part number from this hybrid's lid in the databases of any of the second-hand military parts suppliers, so good chance it's commercial. I think this module is probably part of the motor drive electronics for flap positioning or some other small motion-control function on an airliner.
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Burr-Brown ISO102 Isolation Amplifier
(https://live.staticflickr.com/65535/54086289623_e6aac83e8d_c.jpg) (https://flic.kr/p/2qpqnyT)
Isolation amplifiers are always interesting to me, as I've needed isolated measurements a lot for power electronics work, and there's heavy tradeoffs between bandwidth, common-mode rejection, and size/complexity/expense. This is a relatively low-bandwidth part, at ~70 kHz, which uses capacitive isolation.
The right-hand cavity shown above (with one IC) is the input side, and the left-hand cavity (with two ICs) is the output side. The isolation capacitances are embedded in the ceramic package in between: you can see the two traces from each cavity which run towards the center. The ISO102 datasheet (https://www.datasheets.com/part-details/iso102-texas-instruments-18765040#datasheet) mentions a spiral structure for the isolation capacitances - this would probably show up nicely on an X-ray image, but currently I have no way of getting you a view of that.
Here's the block diagram from the datasheet, showing the general operating principle:
[attachimg=1]
It uses frequency modulation, as you obviously can't pass a DC signal capacitively.
The input side contains a VCO, whose frequency is changed by the input voltage. This 1st VCO's output is then transmitted through the isolation capacitors, and to the output side.
The output side, instead of doing a direct frequency-to-voltage conversion, uses an identical 2nd VCO in the path of a feedback loop. A PLL (https://en.wikipedia.org/wiki/Phase-locked_loop) adjusts the voltage to the 2nd VCO until both frequencies match: the output voltage is then the control voltage to the 2nd VCO, as this will now (theoretically) be the same as the control voltage to the 1st VCO.
This relaxes the linearity requirements on the VCO design, as wrapping it in a feedback loop this way corrects for any systematic weirdness in the VCO's voltage-to-frequency response. As long as the two VCO behaviors match, they can have whatever bizarrely non-linear voltage-to-frequency curves you want and still work correctly.
This scheme doesn't account for part-to-part variation between the two VCO ICs though. Other isolation schemes, such as the HCNR201 analog opto-isolator (https://docs.broadcom.com/docs/HCNR200-HCNR201-High-Linearity-Analog-Optocouplers-DS), do similar things by relying on matched components between input and output sides (in the HCNR201's case, the photodiodes are matched and the control loop is on the input side).
So, here's the VCO IC: this is the single die on the input side, and one of the two dies on the output side:
(https://live.staticflickr.com/65535/54321780711_e76b312fba_c.jpg) (https://flic.kr/p/2qLejS4)
I don't have the time to trace the whole circuit, but you can see a lot of pink resistors with laser-trimming marks. There's also some large metal areas, some of which are probably the capacitors used for the timing functions.
This is the PLL IC, the second of two dies on the output side:
(https://live.staticflickr.com/65535/54320889512_bef51a0cae_c.jpg) (https://flic.kr/p/2qL9KWy)
The resistors are fewer and un-trimmed here (which makes sense, as the VCO is where DC precision matters) and there's some larger capacitors, possibly for the typical PLL charge pump or a loop filter.
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While I figure out the details of some of the more complicated hybrids, here's a quick one that's more about "artistic value" than for interesting circuitry:
Micro Networks MN91410
(https://live.staticflickr.com/65535/54086033971_44f7163d29_z.jpg) (https://flic.kr/p/2qpp4z6)
(https://live.staticflickr.com/65535/54086486015_b8e4f36750_z.jpg) (https://flic.kr/p/2qprnWX)
This has 4 RAM dies inside, along with a 74ACT138 decoder in the center to drive the "chip select" lines based on the upper 2 address bits.
(https://live.staticflickr.com/65535/54086034191_537f8a348e_z.jpg) (https://flic.kr/p/2qpp4CT)
(https://live.staticflickr.com/65535/54086274398_14fc8a72dd_z.jpg) (https://flic.kr/p/2qpqi3o)
(https://live.staticflickr.com/65535/54086274513_1e15873ea6_z.jpg) (https://flic.kr/p/2qpqi5n)
It turned out to be annoyingly difficult to get a good image of a die with repetitive patterns, with the stitching needed, so here's one corner of a memory chip:
(https://live.staticflickr.com/65535/54085153237_6fdb53753c_c.jpg) (https://flic.kr/p/2qpjxL2)
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Burr-Brown DAC650 high-speed digital-to-analog converter
(https://live.staticflickr.com/65535/54574342958_ebf7de90e9_c.jpg) (https://flic.kr/p/2r9xLPy)
This is a 500 Msps DAC: fast even by today's standards, but especially for the early 90's when it was released.
Too fast to be conveniently monolithic like today's high-speed DACs & ADCs:
(https://live.staticflickr.com/65535/54574113421_5bc821aa74_c.jpg) (https://flic.kr/p/2r9wAA2)
If we take a look at the datasheet (http://nic.vajn.icu/PDF/Burr-Brown/DAC650.pdf), it explains what's going on. There's three main dies visible inside:
1. The analog one (larger), with a set of precision current sources and misc. support circuitry such as reference voltage generators. Everything here is relatively slow, and made on a normal silicon process.
2. The fast digital one (smaller), made on a III-V (GaAs) process - this handles the high-speed ECL data inputs, and performs the high-speed switching of the other die's currents into the outputs.
3. A precision resistor array (green-ish), which has some R-2R ladders & termination resistance for the 50Ω outputs.
The block diagram explains pretty well what's going on:
[attachimg=1]
The differential outputs are handled digitally. Rather than having both current sources and current sinks to produce the complementary outputs, there are only current sinks lowering the output voltage relative to the +1V reference. However, there are separate sets of switches for the two outputs, fed with complementary values, so that when more current is sunk from one output less current is sunk from the other output, and vice versa. Let me know if this doesn't make sense.
The actual digital-to-analog conversion is performed with 3 separate methods. The datasheet explains that...
- bits 0-2 select 1 at a time of 7 individual current sources (scaled 1x, 2x, 3x, 4x...),
- bits 3-7 turn on and off binary-scaled current sources (scaled 1x, 2x, 4x, 8x, 16x), and
- bits 8-11 turn on and off identical current sources (scaled 1x, 1x, 1x, 1x), which are fed to an R-2R ladder.
Let's look at the analog die first:
(https://live.staticflickr.com/65535/54574113791_3891197514_c.jpg) (https://flic.kr/p/2r9wAGp)
You can see a lot of self-contained, repeated blocks in the top half. A lot of these look like op-amps, with matched diagonal-connected input transistors and large metal areas for compensation capacitances. There's a couple op-amps in the block diagram above - the others are probably used to set up the current sources. One or two of the non-op-amp blocks must be voltage references as well.
The current outputs exit along the bottom row of pads, and the bottom half is dedicated to these current sources. From staring at the image enough, I'm pretty sure that...
- the small blocks along the bottom edge are cascode transistors for the current outputs (for better precision),
- the brown vertical stripes are the matched current-source transistors that generate the many copies of a reference current - you can see their bottom-edge connections (collectors) being fed to the cascode transistors, and they share one common base voltage (highlighted in red below),
- the red vertical stripes are (trimmed, precision) resistors from the emitters of these transistors to ground, to set their currents.
[attachimg=2]
Most of the current-source source transistors seem to have their collectors connected together in small groups, by the thick block of "collector cross-connection" traces. (One of these traces is highlighted in blue above) I think one reason is to create x1, x2, x4, x8, etc. copies of currents more precisely: one thing I remember from reading Hans Camenzind's IC design book is that you can get better matching between homogeneous rather than heterogeneous structures. Cross-connecting transistors on the left side of the die with ones on the right side the way it's done here, rather than only connecting adjacent transistors, also makes it less sensitive to thermal or process gradients across the die - even more relevant when it's a physically large die like this one.
Next, let's look at the digital die:
(https://live.staticflickr.com/65535/54574448765_f97735cdba_c.jpg) (https://flic.kr/p/2r9yjgP)
The digital inputs enter in parallel along the left and bottom-left sides. There's some latching and decoding of the data, and then the high-speed current switches are the right-most column of transistors. The DC currents from the analog die enter on the top-edge pads, travel to the current switches on the blue-green traces, and then (mostly) join together at the two big differential-output traces at the right-hand edge. There are at least 8 outputs which don't join the common output voltages, as bits 8-11 need to join the output via an R-2R ladder.
This R-2R ladder, plus a resistance to convert these currents to an output voltage, can be seen on the resistor array:
(https://live.staticflickr.com/65535/54574113861_0da5882c4e_c.jpg) (https://flic.kr/p/2r9wAHB)
Notice how it's symmetric, for the two differential outputs. The pad in the very middle, and the large square pads in the top-right and bottom-right are ground. The pads along the left side are the current inputs for bits 8-11, and the light-green blocks between these pads, and between these pads and ground, are the resistors in the R-2R ladder for these top 4 bits. The resistors extended up and down from the center ground pad are the termination resistors, for a total output impedance of 50Ω.
Here's a zoomed-in view of some of the high-speed digital circuitry:
(https://live.staticflickr.com/65535/54573247392_54f761daeb_c.jpg) (https://flic.kr/p/2r9sa9u)
Here's some extra-zoomed views of the current-switch MESFETs, which have larger and larger groups of devices in parallel as the currents get larger:
(https://live.staticflickr.com/65535/54574343848_f976796fce_c.jpg) (https://flic.kr/p/2r9xM5U)
(https://live.staticflickr.com/65535/54574344993_609fd560ee_c.jpg) (https://flic.kr/p/2r9xMqD)
(https://live.staticflickr.com/65535/54574450800_66b3462bf5_c.jpg) (https://flic.kr/p/2r9yjSU)
(https://live.staticflickr.com/65535/54574344988_319b8945e6_c.jpg) (https://flic.kr/p/2r9xMqy)
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MSK 1875H 4x load driver
I got an interesting scrapped avionics board a while back, with this giant hybrid module (and a spot for a 2nd):
(https://live.staticflickr.com/65535/54595149427_3da0cf69e7_c.jpg) (https://flic.kr/p/2rbopRM)
(https://live.staticflickr.com/65535/54596330010_dc06d1dd18_c.jpg) (https://flic.kr/p/2rbusNE)
The CAGE code 19623 is for GE Aviation, and the date codes look pretty recent (2020s, if I'm reading them correctly?) but it's all pretty simple stuff, could've been designed 30 years ago for all I know: a couple MOSFETs, some relays & through-hole passives, etc.
(https://live.staticflickr.com/65535/54596219504_c8bb83390c_c.jpg) (https://flic.kr/p/2rbtTXo)
Let's open the lid of the hybrid module:
(https://live.staticflickr.com/65535/54596330015_a903dbe347_c.jpg) (https://flic.kr/p/2rbusNK)
Damn, that's cool.
You can see that there's 4 roughly identical sections, one in each corner. Each one has a very large power MOSFET, plus a current sense resistor and some diodes.
(https://live.staticflickr.com/65535/54596022231_134b991691_c.jpg) (https://flic.kr/p/2rbsTj8)
Looking at the circuitry inside the module in more detail, it also fits the theme of "simple design that could've been done 30 years ago". The 4 ICs in the common section down the middle are, in order, a CD4001 quad NOR gate, a 74HC03 quad NAND gate (with open-collector outputs), a CD4030B quad XOR gate, and an LM139 quad comparator.
(https://live.staticflickr.com/65535/54596335890_91426cc2d6_c.jpg) (https://flic.kr/p/2rbuuy3)
(https://live.staticflickr.com/65535/54596221464_3ecfe57ff4_c.jpg) (https://flic.kr/p/2rbtUxb)
(https://live.staticflickr.com/65535/54596027631_2753952d57_c.jpg) (https://flic.kr/p/2rbsUVe)
(https://live.staticflickr.com/65535/54596221619_bd8332c4e3_c.jpg) (https://flic.kr/p/2rbtUzR)
Each of the 4 repeated sections also has an MC14538 dual monostable timer, and a 74ALS00 quad NAND gate, plus a mystery 3-terminal IC - by its connections, I'm 99% sure this is some kind of 5V regulator, a 78L05 equivalent:
(https://live.staticflickr.com/65535/54595155337_6bffd23de8_c.jpg) (https://flic.kr/p/2rborBF)
(https://live.staticflickr.com/65535/54596221539_62036297f8_c.jpg) (https://flic.kr/p/2rbtUyt)
(https://live.staticflickr.com/65535/54596027551_cb61fcac7e_c.jpg) (https://flic.kr/p/2rbsUTR)
Now, what's the actual circuitry doing?
[attachimg=1]
We can see that this is a load driver, meant for turning on and off valves, heavy-duty contactors, fixed-speed DC motors, or other similar things. Each of the 4 channels has 2 redundant DC power inputs, which are diode-OR'ed together, and then switched by the power MOSFET (Q3). The power path is highlighted in red.
The only way in which the 4 almost-identical channels differ, is that one of the channels doesn't have the redundant-power diodes.
Basic operation
Each channel is enabled through a combination of 3 NAND gates (U5), with one used as an inverter. I can't figure out a specific pattern to this, but I assume it provides flexibility similar to the active-high and active-low enable pins on the MC14538 (https://www.onsemi.com/pdf/datasheet/mc14538b-d.pdf), for example. When the load is supposed to be enabled, the output of U5D goes high, and this turns on Q2, which pulls down the gate of Q3 (P-channel power MOSFET) and turns on the load.
Output state sensing
U4B and associated circuitry senses the output voltage, and provides an "output on" sense. This gets XOR'ed with the "output enable" signal from U5D by U3C, so that U3C's output goes high when there's a mismatch: the load is turned on when it's not supposed to (power stage has failed short) or the load is turned off when it's not supposed to (shorted output, or power stage has failed open).
Over-current protection
The other source of faults is from the current sense, highlighted in blue at the top-left. Q5 and Q5 act kind of as a sensing current mirror, where the voltage across current sense resistor R20 is divided by R23 to set a current through Q4, which is then level-shifted through a cascode (Q6) and down to ground-level to create a voltage through R29. I've seen this scheme used in LED drivers, as it's a nice simple way to level-shift small analog signals that are sensed on the high-side. However, R25 and R24 make this a little more complicated: they "steal" current from Q4's emitter, and therefore make the sensed current look smaller than it actually is.
I'm not sure what their values are, as it's impossible to measure all this accurately in-circuit: so it's possible that R24 & R25 are so large as to be negligible in normal operation and just act as a pull-down in edge cases. But if they do sink significant current away from Q4, then the combination of R24 & R25, and Q7's Vbe threshold, acts as a threshold for the over-current detection. If so, then R24 & R25 actually form a voltage-dependent over-current threshold: the larger the DC supply voltage, the more current sunk by R24 & R25, and so the higher the load current has to be to trigger the over-current detection.
Once an over-current is detected by Q7 turning on, this triggers timer U6B. The connection from U6B's output to its "Clk+" input (or "A" input, in the datasheet) prevents it from being re-triggered while the timer is running. When U6B's time expires, it triggers U6A, which has the same type of "anti-re-triggering" connection. While U6A is on, it turns on Q1, which turns off Q2 and therefore forces the power switch off.
I think U6A provides an automatic "back-off timing" for the over-current protection, where an over-current causes it to turn off for XXX ms and wait, before trying to turn back on again. I don't understand what U6B is doing, though: U6A isn't triggered until U6B is done, which made me think it might be a "minimum over-current time" discriminator (as in, an over-current has to be present for > XX ms before the fault is triggered), but once U6B is triggered, there's no way to prevent U6A from triggering. So I have no idea what the dual-timer setup here is supposed to be doing.
Fault output indicator
The NOR gate (U1B) takes in both over-current-timer outputs, and so its output is high (normal state) only if both timers are off (no over-current is active).
The outputs from this "over-current combination" gate (U1B) and the "output state doesn't match output command" gate (U3C) are both fed to a NAND gate (U2D). All this circuitry is duplicated on the other 3 channels, and the outputs of all the NAND gates are connected together (as they're all open-collector) to provide some kind of common "fault indicator" output on pin 21.
Another thing I don't understand, though, is how this fault logic operates. The output of U3C is high only in the case of a fault, but the output of U1B is low only in the case of a fault. This means that the output states of U2D don't make sense in any coherent way, either with an active-high or active-low fault output.
I double-checked all the connections here & IC part numbers but couldn't find any issues. The only thing I can think of is that maybe U3, labeled "CD4030B" on the metal layer, is actually a CD4077 XNOR gate with a mis-labeled metal mask. (For low-speed stuff like this I'd expect both the XOR and XNOR to use the same doping masks, but slightly different metal layers to add an optional inversion at the output)
Control power
[attachimg=2]
Nothing exciting here: the digital logic common to all channels shares an external supply pin, while the LM139 has its own supply pin for some reason. The per-channel 74ALS00 and MC14538 are powered from their own independent 5V regulator, with one per channel. This is the mystery IC, labeled "LM148D-5", which seems like a generic 3-terminal fixed linear regulator.
One final note: if you look at the board again, you can see the two bridge rectifiers which provide the 2 redundant DC power supplies for the load driver channels. Having 2 redundant power buses is pretty normal in commercial aircraft, I believe. (If you're wondering why there's only 3 connections to the bridge rectifier, I think the small through-hole diodes on the board are used together with these to provide some kind of weird rectification scheme I haven't bothered tracing out yet)
(https://live.staticflickr.com/65535/54596215624_82e72e3e78_z.jpg) (https://flic.kr/p/2rbtSNu)
Anyways, hope you enjoyed, and let me know if you have any insights on the weirdness of the fault logic.
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(This application note (National Semiconductor # 1696), for the LM5022 LED driver, (http://application-notes.digchip.com/006/6-9398.pdf) is where I first saw this current-sense level-shifting method used. They use a TL431 there to set a precise bias current through the diode-connected transistor, but that's not strictly necessary depending on your precision requirements.)
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Nice MS Kennedy module there. They got acquired by Anaren, who was later acquired by TTM technologies. I've worked with their module designers before, good guys overall. That was probably a custom module for just the one manufacturer.
I don't think the LM142 is a linear regulator. I can't see a bandgap or other way of generating a stable reference voltage. Given a couple resistor dividers I note, maybe a virtual ground? I'd really have to trace out the circuit to drill down to its exact usage.
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Interesting, good to know - it's possible it's expecting the regulation was happening elsewhere, and so this was just driving a fixed ratio. Maybe, for example, the module designers know it's getting a regulated +10V for the LM139, so you can divide that in half and feed it to the digital chips to get a consistent-enough 5V.
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(This application note (National Semiconductor # 1696), for the LM5022 LED driver, (http://application-notes.digchip.com/006/6-9398.pdf) is where I first saw this current-sense level-shifting method used. They use a TL431 there to set a precise bias current through the diode-connected transistor, but that's not strictly necessary depending on your precision requirements.)
I have not seen it in older designs even when dual transistors were more commonly available; Instead differential pairs were used with the emitters tied together, but it amounts to the same thing.
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LM142 is a linear reg but not exactly 78xx equivalent and not bandgap. As far as I see, the two transistors in the top left corner are the zeners and the bias PNPs are near the VIN pad (middle left). You can also see the epi-FET along the left edge.
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(This application note (National Semiconductor # 1696), for the LM5022 LED driver, (http://application-notes.digchip.com/006/6-9398.pdf) is where I first saw this current-sense level-shifting method used. They use a TL431 there to set a precise bias current through the diode-connected transistor, but that's not strictly necessary depending on your precision requirements.)
(https://www.eevblog.com/forum/projects/de-capping-circuit-analysis-of-hybrid-modules/?action=dlattach;attach=2594145;image)
U2 is a TL431?
I don't understand how that works. A TL431 with the control pin to anode (GND) does nothing. ???
Control pin to Anode is how they measure IOFF of a TL431 in fig.9 of the datasheet (typical 2.6nA).
https://www.st.com/resource/en/datasheet/tl431.pdf (https://www.st.com/resource/en/datasheet/tl431.pdf)
Even if it were to be a schematic typo, and the control pin is in fact supposed to be tied to the TL431 Katode (as a 2.5V shunt regulator), still won't work. If control pin is tied to Katode, then the TL431 will be in thermal shutdown at all times, because V drop on the LED(s) is bigger than 2.5V.
Then, in the rest of the AN1696, the U2 (TL431) is not mentioned at all, not even in the BOM.
Is U2 a schematic typo (shouldn't be there at all), or is that some unusual TL431 trick that I don't understand?
Later Edit
------------
I've searched for the TI's AN-1605 (mentioned in this AN1696 by NS), and in the BOM of the AN-1605 the U2 part number is "Not Used". So, I guess U2 is a schematic typo/leftover that shouldn't be there? :-//
https://www.ti.com.cn/cn/lit/ug/snva229a/snva229a.pdf (https://www.ti.com.cn/cn/lit/ug/snva229a/snva229a.pdf)
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Doh, the control pin of TL431 tied to anode instead of cathode is a typo that went in two Application Notes.
Then, the Rz is not zero ohms, but the TL431 is optional, so when a TL431 is installed, the 0 ohm Rz has to be replaced with an Rz of a proper value.
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Burr-Brown ISO107 isolation amplifier with power supply
(https://staging-jubilee.flickr.com/65535/54664357677_22815cd9d7_z.jpg) (https://flic.kr/p/2rhv84t)
Unlike the ISO102 that I looked at earlier (https://www.eevblog.com/forum/projects/de-capping-circuit-analysis-of-hybrid-modules/msg5866047/#msg5866047), this part is different because it also provides isolated power to its input side - you don't have to figure out how to power both your input-side circuitry and the input side of the isolation amplifier itself. You might notice the package is unusually thick...
After a couple carefully-targeted whacks with a screwdriver and rubber mallet, you can see why:
(https://staging-jubilee.flickr.com/65535/54664357912_1d1c6a4220_c.jpg) (https://flic.kr/p/2rhv88w)
There's a giant ferrite core in there! It's used as a transformer in a switch-mode power supply that provides the isolated power to the input side. The way they've used it too is pretty clever. Normally, assembling a transformer from a wide & flat core like this one involves wrapping a lot of windings, probably by hand, and then stripping/tinning/soldering the ends down to the substrate. This second step is particularly hands-on and error-prone, and hand-soldering directly to a ceramic substrate is probably harder when trying to avoid cracking it. So it's impressive that they've side-stepped all these difficulties by using what they've already got available, which is wire-bonding. Every one of the windings consists of a very long wire-bond extending over the top of the core, and then the bottom halves of each winding are formed by traces inside the ceramic substrate running underneath the core.
On the output side, you can see 2 ICs plus 2 discrete transistors (for driving the transformer) buried in the goop, doing a center-tapped push-pull:
(https://staging-jubilee.flickr.com/65535/54665186136_482f1fa559_c.jpg) (https://flic.kr/p/2rhznkf)
The input side has one IC, plus 4 discrete diodes for rectifying the transformer output for positive & negative voltages from a center-tapped secondary winding:
(https://staging-jubilee.flickr.com/65535/54668309429_7b8c6e5fa3_c.jpg) (https://flic.kr/p/2rhRnM8)
According to the datasheet (https://www.datasheetarchive.com/datasheet/ISO107/Burr--Brown), the actual signal here is capacitively-isolated, with capacitances formed by the metal patterns within the ceramic. Because you can only send an AC signal through the isolation capacitances, there has to be some sort of modulation scheme which generates an AC signal to transmit across the isolation barrier. The ISO102 generated a variable frequency based on the input voltage, but here, the power supply and the modulation/de-modulation circuitry are synchronized at a fixed frequency, to avoid interference between the two. (I'm guessing that translates in practice more to "make the interference predictable so it can be ignored") So here, the duty cycle is modulated instead.
[attachimg=1]
Here's one of the ICs on the output side:
(https://staging-jubilee.flickr.com/65535/54665417373_0e78b03ee2_c.jpg) (https://flic.kr/p/2rhAy56)
This seems to be the power supply IC, which contains an externally-synchronizable 800 kHz oscillator, logic for generating the power transistor drive waveforms, and some pre-driver power transistors at the bottom-right corner.
This is the other IC on the output side - the PWM demodulator:
(https://staging-jubilee.flickr.com/65535/54665518520_fe785f278e_c.jpg) (https://flic.kr/p/2rhB591)
Finally, this is the single IC on the input side - the PWM modulator:
(https://staging-jubilee.flickr.com/65535/54665518510_212bf2bc48_c.jpg) (https://flic.kr/p/2rhB58Q)
Its role is significantly different than the PWM demodulator, but notice that the left half of the die is identical between the two - there must be a good deal of shared circuitry. The datasheet doesn't go into detail on how it works, but it's possible that internally, the modulator is driven by a feedback loop wrapped around a demodulator (matched to the one on the output side), rather than trying to make a precise "feed-forward-only" PWM modulator.
All the ICs have plenty of on-chip capacitors (the large metal areas), and resistors, some of them laser-trimmed - the datasheet specifically mentions that trimming is needed to match the modulator with the demodulator. Both the PWM modulator/demodulator ICs have lots of un-bonded test pads, some of them with scratches showing that they were probed during testing (possibly as part of the laser-trimming process). The modulator IC also has a couple test structures which you can see floating in the empty space vaguely near the top-right, unconnected to anything else: one for on-chip resistors, and one for a transistor.
I'm curious about how exactly the PWM modulator is implemented, and there's few enough transistors that the idea of tracing the circuitry doesn't make me want to run away screaming from the tediousness - but I'm going to leave that for a different time.
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Burr-Brown SDM863 Data Acquisition System
(https://live.staticflickr.com/65535/54664358752_da31809846_c.jpg) (https://flic.kr/p/2rhv8o1)
Here, "data acquisition system" means that it's an ADC, preceded by muxing of a lot of input (differential) channels with adjustable gain. Here's a block diagram from the datasheet: (https://www.alldatasheet.com/datasheet-pdf/view/88315/BURR-BROWN/SDM863K.html)
[attachimg=1]
The package is a slightly unusual SMT or socketed pad array usually reserved for old CPUs. You can see the multiple dies up-close here:
(https://live.staticflickr.com/65535/54665187946_d099d5601d.jpg) (https://flic.kr/p/2rhznSs)(https://live.staticflickr.com/65535/54665519145_2a770a67ed.jpg) (https://flic.kr/p/2rhB5jM)
Each die (unsurprisingly) corresponds roughly to one functional block, so let's look at them one by one:
[attachimg=2]
1. Input multiplexer
(https://live.staticflickr.com/65535/54665419363_8e0fc686e9_c.jpg) (https://flic.kr/p/2rhAyEp)
This is a dual 8:1 mux made by PMI (Precision Monolithics Inc.), roughly divided between left and right sides. Each of the large blue rectangles on the edges is a FET switch, and the wide flat pink rectangles in the center column look like multi-emitter bipolar transistors used to decode a common set of control signals (the metal-layer wiring spiraling up the center-left, over the top, and down the center-right) and selectively activate each channel.
2. Instrumentation amplifier
(https://live.staticflickr.com/65535/54664360497_1389bf5091_c.jpg) (https://flic.kr/p/2rhv8U6)
This is actually the only die in this module made by Burr-Brown! You can see a lot of laser-trimmed resistors, and two amplifiers - one in the bottom half, and one in the top half. Each has a differential pair, 4 transistors (blue squares) cross-connected in a square pattern, for thermal & process gradient cancellation. The datasheet shows how this stage works:
[attachimg=3]
...but judging from the die I don't think the two buffers are made from fully independent op-amps.
3. Sample and hold
(https://live.staticflickr.com/65535/54665520605_a80110795c_c.jpg) (https://flic.kr/p/2rhB5KX)
Here's another one from PMI. There's no obvious features I can pick out - there are two larger transistors in the bottom-right and center-left, so I don't know which one (if not both) is the sampling switch. The sampling capacitor has to be added on an external pin, as its value depends on sampling rate, so there's no on-chip sampling cap to see here.
4 & 5. ADC
(https://live.staticflickr.com/65535/54664360762_f1a13a9a11_c.jpg) (https://flic.kr/p/2rhv8YE)
(https://live.staticflickr.com/65535/54665419463_487f0baa90_c.jpg) (https://flic.kr/p/2rhAyG8)
The successive-approximation(?) ADC (https://en.wikipedia.org/wiki/Successive-approximation_ADC) is split up into two ICs - the first seems to be the analog section (DAC & comparator), and the second seems to be the digital section (successive approximation register & logic).
The regular set of repeated resistors (bright green) and surrounding circuitry in the first die seems to be the DAC's resistor ladder (https://en.wikipedia.org/wiki/Resistor_ladder#R%E2%80%932R_resistor_ladder_network_(digital_to_analog_conversion)).
Interestingly, both these ICs are made by Harris. Burr-Brown themselves have only (as mentioned before) manufactured the instrumentation amplifier! It's possible Harris had digital processes (or just fab capacity) that Burr-Brown didn't? You can see a great look at the Burr-Brown ADC574 here from forum member Noopy (https://www.richis-lab.de/ADC02.htm), which shows two dies very similar to these two, also made by Harris.
That's it - hope it was interesting.
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Aydin Vector TC-801 Thermocouple Conditioner for Telemetry System
(https://live.staticflickr.com/65535/53603112520_f8701b8abb_z.jpg) (https://flic.kr/p/2pEHXRb)
Aydin Vector is a company primarily in the telemetry business. After a lot of searching, I finally found a photo of a board containing two of these hybrids (https://www.artisantg.com/TestMeasurement/90623-15/L-3-Aydin-TCC-116-4-Thermocouple-Conditioner):
[attachimg=1]
This is a 16-channel thermocouple input card for a modular telemetry system. The idea seems to be that there's one central controller with an ADC - you add on as many specific types of input modules as you want, and it cycles through each input module, digitizing each one's channel(s) in turn. This module in particular, then, is going to be doing some thermocouple-specific things: amplifying the tiny thermocouple voltages up to a normal signal range, and somehow handling cold junction compensation (https://en.wikipedia.org/wiki/Thermocouple#Reference_junction). Because the board has pretty much nothing on it besides the two hybrids and some resistors & capacitors (probably input protection/filtering), we'll get to see all the magic happen here.
(https://live.staticflickr.com/65535/53602985619_cc79fb7567_z.jpg) (https://flic.kr/p/2pEHj8e)
(https://live.staticflickr.com/65535/53603112525_d55d4a6151_z.jpg) (https://flic.kr/p/2pEHXRg)
...and there sure is some magic, with quite a collection of thin-film resistors.
Overview & explanation
After some probing around with sewing needles for continuity checks, this is how the sections are laid out:
[attachimg=2]
There are 8 identical channels, with the right-most channel chosen as the example. Here's how it works:
[attachimg=3]
Each thermocouple signal enters via two pins at the left. After a couple pull-down resistors and some series filtering, a pair of LTC1012 precision op-amps does differential amplification. All 8 channels are muxed via a single chip (U3, dual 8:1 analog mux), and the differential signal is fed first through a differential-to-single-ended conversion (U4B), and then some offsets are added (U4C). The output is gated by an analog switch (U7A), and exits on a pin at the opposite side of the package.
The offset applied in the final stage comes from a different circuit (U5). The idea behind cold-junction compensation is that a thermocouple generates a temperature reading only relative to the point where you insert its leads into a connector (based on the thermal effects of the different metals touching), so you need to sense the absolute temperature at that connection point using a different method, and add a temperature-dependent offset voltage to the thermocouple reading. U5 does this by generating an offset voltage based on some combination of a -5V reference (U6) and an input from an external pin (via R2 & C3). I'm guessing this is where the cold-junction compensation's temperature sensor is connected externally. The adjacent pin is connected only through R3 to the positive supply voltage, as far as I can tell. Thermistors are a popular choice for cold-junction compensation, but putting a temperature-sensitive resistance directly between these pins might not make sense, depending on your accuracy target, as the supply voltage isn't particularly accurate or stable. So it's possible it's meant to use an external voltage-output temperature sensor IC, and R3 simply provides the power to this sensor. Or maybe the math works out so that the constant offset added by the -5V reference has a much bigger impact on the output than the thermistor's contribution...who knows.
Two additional analog switches are used to ground the mux outputs on command (U7C & D). I have to assume the reason to do this would be to calibrate out the offset added by everything downstream of the mux. There's one last analog switch (U7B), but I couldn't find where it connects.
Control seems to happen through a digital gate array, which I'm assuming communicates to the main controller and selects channels appropriately:
(https://live.staticflickr.com/65535/54339693117_43c09907ce_z.jpg) (https://flic.kr/p/2qMP8AD)
There's a logic chip next to it which looks like a hex inverter, judging by the number of identical channels:
(https://live.staticflickr.com/65535/54341013525_aea6102b8d_z.jpg) (https://flic.kr/p/2qMVU7i)
Interesting features: resistor networks
RN3 and RN6 in the schematic stand out, as they seem to have different bond-wire-selectable sections. Here they are, respectively:
(https://live.staticflickr.com/65535/54340810019_c280884f3c_z.jpg) (https://flic.kr/p/2qMURBz)
(https://live.staticflickr.com/65535/54340817408_3be468a73a_z.jpg) (https://flic.kr/p/2qMUTNY)
In RN3's case, the high feedback resistances for the channel gain are the long, thin sections at the left and right sides. The small "common" or "bridging" resistance (for high gain) comes from the thick sections in the middle.
Next to both of these resistors, there's a long trace on the ceramic substrate which stretches the width of the resistor array. One of the pads for the intermediate sections is also connected with an extra bond wire to this long trace. The idea seems to be that you can set different gains by bonding the long trace to a different tap in the resistor chain.
[attachimg=4]
RN4 and RN5 are also nice to look at:
(https://live.staticflickr.com/65535/54340809484_a40c55bce0_z.jpg) (https://flic.kr/p/2qMURsm)(https://live.staticflickr.com/65535/54339693307_ec59a16a0f_z.jpg) (https://flic.kr/p/2qMP8DV)
The series input resistors on each channel (RN2) seem to be trimmed together, likely to match and avoid degrading CMRR (if they're large values):
(https://live.staticflickr.com/65535/54340809489_ddc104bb84_z.jpg) (https://flic.kr/p/2qMURsr)
RN1 seems like its value(s) should be non-critical, but it's trimmed as well:
(https://live.staticflickr.com/65535/54340817353_b9d15dc061_z.jpg) (https://flic.kr/p/2qMUTN2)
Here's the small-value resistors used for supply voltage filtering:
(https://live.staticflickr.com/65535/54340594971_5eccbb9218_z.jpg) (https://flic.kr/p/2qMTKFR)
...some misc. resistors scattered around the digital section:
(https://live.staticflickr.com/65535/54340594926_9a76c6b2b9_z.jpg) (https://flic.kr/p/2qMTKF5)(https://live.staticflickr.com/65535/54340594956_e5e6264162_z.jpg) (https://flic.kr/p/2qMTKFA)
...and R3 and R4, in no particular order:
(https://live.staticflickr.com/65535/54340809949_c5e434db9a_z.jpg) (https://flic.kr/p/2qMURAn)(https://live.staticflickr.com/65535/54340595016_8de7eb9041_z.jpg) (https://flic.kr/p/2qMTKGC)
Interesting features: reworks
[attachimg=5]
There's a few places where extra capacitors for either power supply or input-signal filtering have been patched in, where it looks like they weren't originally intended to go. Connections to some of them are made through these little ceramic "sticks". The middle example also shows the "+" and "-" inputs of 2 of the quad op-amps being swapped, via more of these "sticks". I'm not sure if this was...
1. a mistake in the design, and this is a prototype copy where it was fixed manually for testing,
2. a mistake in the design, and it was too expensive / low-volume to fix the design, so these reworks were added to every copy in production, or
3. an intentional way to work around congested routing, without adding an extra routing layer for a more complicated and/or expensive process.
Interesting features: die shots
We've already looked at the two digital ICs, but here's the LT1012 op-amp used on each input channel:
(https://live.staticflickr.com/65535/54340809609_e8b8ef981d_z.jpg) (https://flic.kr/p/2qMURuv)
...the quad op-amp used for the common analog circuitry:
(https://live.staticflickr.com/65535/54340594846_3cd930d89c_z.jpg) (https://flic.kr/p/2qMTKDG)
...the dual 8:1 analog mux (made by Analog Devices, but don't know the part number):
(https://live.staticflickr.com/65535/54339692977_d00f14abed_z.jpg) (https://flic.kr/p/2qMP8ye)
...the quad analog SPST switch (same situation):
(https://live.staticflickr.com/65535/54339693207_43da6076ac_z.jpg) (https://flic.kr/p/2qMP8Cc)
...and the AD586 voltage reference:
(https://live.staticflickr.com/65535/54340809874_c71d838e84_z.jpg) (https://flic.kr/p/2qMURz5)
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I wonder why they did not use the LT1112 instead of a pair of LT1012s.
Is there a date code somewhere? Maybe the LT1112 was not available yet.
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Good question. No date codes I could find, except for the "1989" on the AD586 die.
Actually, interesting side note about that AD586: the "B586" on the die made me suspect early on that it was the AD586, but I was having trouble matching up the pinout (hadn't figured out there were separate force and sense pads for the output, and that it was set up in the negative-voltage configuration) so I went looking through the bitsavers databooks. The 1989 ADI databook showed a die image for the AD586 that was similar but definitely not the same as this one. The 1992 ADI databook, though, showed a die image that was identical, down to the "B586" marking. So this particular die comes from sometime >1989 (only a little bit younger than me, hah).
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The quad opamp is interesting. The two layers of metal and general appearance are similar to AD586, but there is no AD logo and I failed to find any match in the 1992 amplifier databook. The chip uses some sort of junction isolated complementary bipolar process: there are no lateral PNPs, but some vertical transistors are made in "wells" which have a fourth terminal biasing them to one of the supply rails. BTW, do you know which rail is positive and which negative?
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I think the bottom supply pad is positive and the top is negative...but I'm not 100% sure. The bottom one connects to the gold area under the die, and is V+ for all the other circuitry, while the top one is V- for the other circuitry. So either this was a routing mistake and the module doesn't work (which fits with the swapped inputs and reworks on those), or the substrate is tied to the positive supply rather than negative supply (which fits with the unusual process?).
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US patent 4,969,823 filed by Analog Devices in 1988 describes a junction isolated complementary bipolar process with N-doped substrate biased to V+ and P-doped epitaxial layer and wells for NPN transistors.
[attachimg=1]
Possibly another hint that this is an AD chip. But AFAIK by the 1990s all big players in high end analog (AD, LT, TI, NS) had some sort of complementary bipolar processes and I don't know them all and how to tell them apart.
edit
Wait, the image above doesn't show separate wells for NPNs. Either it's some other process or maybe it needs those local connections for some reason. Two metal layers aren't making it easy, but I will see if I can figure out this circuitry and which transistors are which polarity.
edit edit
Actually, nothing stops them from running N isolations between NPNs and cutting that P-epi into fragments, for whatever reason.
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Good luck! You have more patience than me, the dual overlapping metal layers are such a pain - I started trying to follow the connections on the AD586 but had to give up :)
Also while finishing up checks on another hybrid, I just ran across an LTC1050, which also has a positive substrate bias in-circuit. Maybe there's something to be learned by comparing the LTC1050 with the mystery quad op-amp.
(https://live.staticflickr.com/65535/54702388969_df19cd5da1_z.jpg) (https://flic.kr/p/2rkS3rp)
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I have a question you guys might have some insight on. When I use something like a DRV8837 bridge motor driver, it has a metal pad in the center used for heat dissipation. This is supposed to be soldered to a ground plane. They never say much about it electrically, but I assume it's the actual metal carrier for the die. What might one expect if it were tied to Vcc or even a voltage below ground? Can the silicon be considered a good insulator? Or would there even be a general rule?
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Unless the documentation says otherwise, it is safest to assume that the die is soldered to the metal pad, i.e. the pad is connected to the substrate. For the majority of parts, this would be connected to the most negative supply for the IC.
This pad connection should really should be specified in the datasheet.
John
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If it is connected to the silicon substrate (safe to assume as JohnG said), then what would happen if you connected it to Vcc (or any voltage more positive than Gnd) is that it would forward-bias some or all of the parasitic diodes between the substrate and the various transistors & wells internally, and do all kinds of wacky shit including almost definitely frying the chip. You might get away with connecting it to something more negative than gnd, but depends on the breakdown voltages, what your supply voltage is compared to the max ratings, etc.
Anyways, back to hybrids and/or mystery op-amps...
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Good luck! You have more patience than me, the dual overlapping metal layers are such a pain - I started trying to follow the connections on the AD586 but had to give up :)
It's annoying, but I have done AD587 and AD588 in the past, there are full schematics somewhere on this forum. Not sure if I will manage 100% of your opamp, but so far it looks like the input stage is an H-bridge - two diamond buffers driving two ends of a resistor and their collector currents make the output of the input stage. That probably goes to some current mirrors and a unity gain output stage, like in current feedback amplifiers, but not sure yet. Whatever it is, it was likely advertised as a quad high-speed, high slew rate voltage feedback opamp.
A little unexpected type for a thermocouple amplifier, but it was after the mux so they may have wanted speed to quickly scan through all those channels and the precision microvolt job is already done by those LT1012.
Also while finishing up checks on another hybrid, I just ran across an LTC1050, which also has a positive substrate bias in-circuit. Maybe there's something to be learned by comparing the LTC1050 with the mystery quad op-amp.
That's CMOS, a different technology. It can be done either way (keywords: "N-well" or "P-well"), though P-well (N substrate biased to V+) seems more common in analog for whatever reasons.
I have a question you guys might have some insight on. When I use something like a DRV8837 bridge motor driver, it has a metal pad in the center used for heat dissipation. This is supposed to be soldered to a ground plane. They never say much about it electrically, but I assume it's the actual metal carrier for the die. What might one expect if it were tied to Vcc or even a voltage below ground? Can the silicon be considered a good insulator? Or would there even be a general rule?
Doped silicon is not an insulator at all and the substrate (the bulk of the die) is often connected internally to GND or one supply rail or another, so soldering it to a different rail will do nothing good. Sometimes the datasheet says that the pad is floating, but even then GND may be a good idea for EMI reasons.
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Ahh CMOS, ok, that's what I get for being lazy and not bothering to read the datasheet. I'm not good enough at this to tell apart weird-bipolar from CMOS unless there's some super obvious interdigitated gate structures.
Anyways, speaking of the LTC1050, this additional hybrid ended up being unexpectedly simple, so in a 2-for-1 deal, here's...
BI 34090218 mystery module
Outside:
(https://live.staticflickr.com/65535/54701343122_8e308ddcde_z.jpg) (https://flic.kr/p/2rkLFxy)(https://live.staticflickr.com/65535/54702505790_5038e64d97_z.jpg) (https://flic.kr/p/2rkSDay)
Inside:
(https://live.staticflickr.com/65535/54701343127_1f6b227c06_z.jpg) (https://flic.kr/p/2rkLFxD)(https://live.staticflickr.com/65535/54702379543_957d8778f7_z.jpg) (https://flic.kr/p/2rkRZCT)
The IC at the left is an LTC1050 op-amp - the whole right third is taken up by the compensation capacitor:
(https://live.staticflickr.com/65535/54702388969_df19cd5da1_z.jpg) (https://flic.kr/p/2rkS3rp)
The IC at the right is a PMI SW-201 or SW-202 quad analog switch:
(https://live.staticflickr.com/65535/54702155036_e5d1c156c4_z.jpg) (https://flic.kr/p/2rkQQU5)
The two large rectangles in the middle are resistors, covered with polyimide. Luckily, the coaxial lighting on the microscope penetrates right through that, and we can get a good look at the resistive traces:
(https://live.staticflickr.com/65535/54702169831_8defdfb36b_z.jpg) (https://flic.kr/p/2rkQVia)
At first I was wondering where the damage on the left edge came from, and then realized it's a rough-looking form of resistance trimming. If you look carefully, you can see some smaller "bypass" paths in between the numbers on the left edge, some of which get cut to increase the resistance slightly.
There's not a lot of circuitry in there, so tracing it was surprisingly quick:
[attachimg=1]
The op-amp forms an integrator (with the ceramic cap visible on the inside, at the far left), which has many possible inputs on different pins, selectable with the analog switch. I'm not sure what R5 and R6 are doing (the two large polyimide-covered resistors) with their low values: is this supposed to serve as the low side of an external voltage divider? A current-to-voltage conversion for an external current source?
Overall, the only thing I can think of is that this looks like part of a multi-slope ADC (https://en.wikipedia.org/wiki/Integrating_ADC#Multi-slope_run-up), where various reference and input voltages are integrated sequentially. However, it's also possible that there's supposed to be a DC feedback resistor(s?) added externally, such as between pins 3 and 13, and it has a more general-purpose use. This falls into the category, like some of the TRT hybrids earlier in the thread, where the circuit is application-specific enough to not be an obvious general-purpose building block, but not application-specific enough to be obvious where it's meant to be used.
The op-amp is given an internally-regulated supply voltage that's lower than what the analog switch sees. Here's what R3 & R4, the series power supply resistors, look like:
(https://live.staticflickr.com/65535/54702171556_487bba9a0e_z.jpg) (https://flic.kr/p/2rkQVNU)
This is R1, the input-bias-current-balancing resistor:
(https://live.staticflickr.com/65535/54702171546_0cd344e8dd_z.jpg) (https://flic.kr/p/2rkQVNJ)
...and this is R2, the inverting-input resistor pair:
(https://live.staticflickr.com/65535/54702171551_6aec5d0b56_z.jpg) (https://flic.kr/p/2rkQVNP)
The last interesting thing I noticed is that the diodes used to clamp the op-amp's inverting input look a bit unusual. There's two bond pads used but they both connect to the same place: maybe a dual diode, with both connected in parallel here. Can't recognize a Schottky or other special diode structures off the top of my head, but maybe someone else does?
[attachimg=2]
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Is BI Beckman and did that go in a meter or some piece of measurement equipment?
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Good question - I only know them as TT/BI, for resistor arrays and trimmers that I sometimes use in designs. Looks like you're right and "BI" stands for "Beckman Industrial": https://www.ttelectronics.com/products/passive-components/resistors/heritage/ (https://www.ttelectronics.com/products/passive-components/resistors/heritage/)
No idea about end-use, as I got it as NOS. The metal encapsulation and everything is a bit more than it would need even for high-end test equipment, so my best guess is aerospace/military/heavy-industrial.
Edit:
Wait, here's a datasheet for BI's line of "military-grade hybrid microcircuits". I guess their own part number is the 165-1766-0, and the "165" is their custom hybrid series: https://www.alldatasheet.com/datasheet-pdf/pdf/850180/BITECH/165.html (https://www.alldatasheet.com/datasheet-pdf/pdf/850180/BITECH/165.html)
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The quad opamp is interesting. The two layers of metal and general appearance are similar to AD586, but there is no AD logo and I failed to find any match in the 1992 amplifier databook.
Well, I must be going blind, because it's right there in this exact book :palm:
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MIL-STD-1553 Transceivers, Part 1: National Hybrid NHI-1544FP
Something that I've encountered a lot in looking at older aerospace electronics (https://dcstraney.wordpress.com) is the MIL-STD-1553 serial interface (https://en.wikipedia.org/wiki/MIL-STD-1553). This was meant as a standard way for avionics to talk to each other - the military and space equivalent of ARINC 429 (https://en.wikipedia.org/wiki/ARINC_429) on airliners. The higher-level protocol gets somewhat complex with broadcast vs. point-to-point messages, bus controllers, etc., but the physical layer is straightforward. It uses bipolar differential signalling on a twisted pair, AC-coupled through a transformer to remove any DC grounding issues (Manchester encoding (https://en.wikipedia.org/wiki/Manchester_code) is used to make the AC-coupled pulses timing-dependent rather than level-dependent).
There are a few hybrid modules from different manufacturers which contain an entire physical-layer transmitter and receiver, minus the transformer - the digital transmitter-inputs and receiver-outputs from these are then connected to controllers which handle the higher-level communications protocol. The pinout seems to be a de facto standard, so this makes a great opportunity for comparing a couple different functionally-equivalent modules side by side, to see how different engineers went about solving the same problems differently!
The first one we're looking at is from National Hybrid:
(https://live.staticflickr.com/65535/55053209015_14f84118b1_z.jpg) (https://flic.kr/p/2rSS61T)
We can see that it's fairly complicated inside, with a lot of different parts:
(https://live.staticflickr.com/65535/55053209020_fbfe233e03_z.jpg) (https://flic.kr/p/2rSS61Y)
(https://live.staticflickr.com/65535/55052865186_83a3541a2a_z.jpg) (https://flic.kr/p/2rSQjNN)
The ICs inside are all "generic building block" parts:
[attachimg=1]
74LS00 quad 2-input NAND gate
(https://live.staticflickr.com/65535/55051958477_55b96066d9_z.jpg) (https://flic.kr/p/2rSKFgT)
74LS10 triple 3-input NAND gate
(https://live.staticflickr.com/65535/55053115879_3f76d51743_z.jpg) (https://flic.kr/p/2rSRBk6)
74LS26B quad 2-input NAND gate, open-collector outputs
(https://live.staticflickr.com/65535/55051958327_ef3d063ddf_z.jpg) (https://flic.kr/p/2rSKFei)
Op-amp of some kind (2 copies)
(https://live.staticflickr.com/65535/55052862321_5f1b313ed2_z.jpg) (https://flic.kr/p/2rSQiXp)
LM117 adjustable 1A linear regulator
(https://live.staticflickr.com/65535/55051958482_89dbccabe5_z.jpg) (https://flic.kr/p/2rSKFgY)
TL431 2.5V shunt voltage reference
(https://live.staticflickr.com/65535/55052862286_dbb5e188a8_z.jpg) (https://flic.kr/p/2rSQiWN)
LT119 dual fast comparator (photo from a different module of mine)
(https://live.staticflickr.com/65535/54328396527_a7e9a4b54f_z.jpg) (https://flic.kr/p/2qLPevR)
...plus a couple copies of trimmed resistors that are interesting-looking, and 2 of the power transistors:
(https://live.staticflickr.com/65535/55053115714_c5ebdca03a_w.jpg) (https://flic.kr/p/2rSRBhf)(https://live.staticflickr.com/65535/55053206335_43c79e91fb_w.jpg) (https://flic.kr/p/2rSS5dF)(https://live.staticflickr.com/65535/55053206440_ccf5d08716_w.jpg) (https://flic.kr/p/2rSS5fu)
For the circuitry, let's look at the receive side first, as it's the simplest:
[attachimg=2]
There are two power supplies: Vcc is +12-15V, and Vee is -12-15V.
- The differential inputs enter at the left, go through series resistors for current-limiting, and have the differential voltage clamped to roughly +/- 1.5V by D5-D8.
- Next, one op-amp in a classic difference-amplifier configuration (U5) converts the clamped differential input into a single-ended signal.
- This signal is then fed through a 3-pole low-pass filter: first, a single-pole RC (R36 & C10), then a 2-pole Sallen-Key type (R37 onwards). The Sallen-Key topology requires a voltage buffer, and so here a single discrete transistor (Q11) is used as an emitter follower. This must be to filter out EMI-induced noise that could otherwise appear as false transitions.
- The DC level shift introduced by this discrete-transistor buffer doesn't matter, as the signal is then AC-coupled through C13, and then fed to a pair of comparators (U6). These compare against separate positive and negative thresholds for the differential input (remember that the input signal is bipolar), and produce 2 separate digital outputs. The data rate is 1 Mbps, which translates to 1 µs per bit, and there can be up to 2 transitions in this time, because of the Manchester encoding - so the comparator has to be significantly faster than this to work correctly. The LT119 is specified at an 80 ns delay. I'm not sure exactly what D9 & D10 are for, on the comparator inputs, as comparator are normally meant to saturate the input transistors. Their actual effect depends on the relative values of R40 vs. R42-R50. The TL431 is used here to generate the negative threshold, and the linear regulator (discussed further in the transmit section) is used to generate the positive threshold.
- Finally, a couple NAND gates are used to gate the two digital outputs based on a separate "Enable" ("Strobe") input. There's also some inverters here made from NAND gates: the output pins can optionally be wirebonded to their outputs instead. The reason for this seems to be different behaviors when the MIL-STD-1553 bus is idle (~0V differential). According to a DDC datasheet, the "Smiths-compatible" transceivers put both (Rx Data) and !(Rx Data) high when there's no input, while the "Harris-compatible" transceivers put both (Rx Data) and !(Rx Data) low in the same situation. Inverting both digital outputs (by bonding to U7B & U7C outputs) and swapping them is equivalent to changing between these two styles of idle-level outputs. This makes it easy for National Hybrid to manufacture two models of transceivers, one for each "idle style", which are identical except for where a couple wirebonds are placed.
Next, the transmit section:
[attachimg=3]
You can see here where the LM117 is used, to produce an internal supply of roughly 6.6V, which is used as a (not very accurate) reference point in a few places.
There's a lot going on here, so let's step through section-by-section:
- Input logic: The mess of NAND gates here decodes 3 inputs - (Tx Data In), !(Tx Data In), and Tx Inhibit - and produces 3 outputs. U1B & U1D produce complementary open-collector outputs that are used to modify analog setpoints downstream, and are never active at the same time. U1C produces an "enable" output, which either powers on or powers off the output driver. When both "Tx Data In" inputs are complementary, the output driver is enabled and its analog setpoint is modified accordingly. When the "Tx Data In" inputs are either both high or both low (not a valid state for complementary inputs), the output driver is powered off. The output driver is also powered off whenever the "Tx Inhibit" input is high.
- Output voltage setpoint generator: A single op-amp is used here in a simple inverting or non-inverting configuration (depending on how you want to think about it), to generate the setpoint for the output voltage.
- When the digital input data is low, U1B's output is low, and its open-collector output pulls the op-amp's "+" input to ground. This forms an inverting amplifier, where the equivalent input voltage is Vaa (~ +6.6V), so the op-amp's output goes to a negative voltage.
- When the digital input data is high, U1D's output is low, and its open-collector output pulls the intersection of R25 & R26 to ground. This forms a non-inverting amplifier, where the equivalent input voltage is a scaled (by R19 & R29) copy of Vaa, so the op-amp's output goes to a positive voltage.
- Filters: The output voltage setpoint goes through a 3-pole low-pass filter here, identical in structure to the 3-pole low-pass in the receive section. As before, a single-pole RC filter is followed by a 2-pole Sallen-Key topology using a single emitter-follower transistor as the voltage buffer. MIL-STD-1553 has specific specifications for slew rates of the outputs, which is probably for both EMI (less noise induced in adjacent cabling) and signal integrity (less issues with reflections in cabling stubs) reasons. This filter likely determines the shape of the output transitions, and so makes the waveforms meet the target specifications.
- Bias switch: When the output driver is supposed to be powered off, U1C's open-collector output is pulled to ground. This turns off Q8, since the Q7-Q8 connection means that Q8's base needs to be about 2*Vbe above ground to turn on. When the output driver is supposed to be powered on, R13 pulls up Q8's base, and allows Q8 to both turn on the common-emitter Q9 and common-base Q7 with the same collector/emitter current. Q9 applies +6.6V to the left side of R17 & R17b, which supplies positive bias to the output driver's feedback circuitry, as we'll see soon. Q7 turns on Q5, which switches negative bias (Vee) to the output driver as well.
- Voltage amplifier & output driver: This part is the most complicated. Because of the two differential outputs, there are two identical copies of the output driver - the second one is shown at the bottom-right of the schematic.
- The simplest part is the class-AB power stage, made from Q1 and Q2. The linear output stage, instead of just switches from Vcc & Vee, is needed here because of the defined transition shaping created by the earlier filter, and possibly smaller voltage levels as well? Q1 & Q2 have their idle bias current set by the "Vbe multiplier" (https://en.wikipedia.org/wiki/Rubber_diode) made from Q3, R5, and R6.
- On the positive output driver, the voltage at the emitter of Q6 is set by the setpoint voltage. "Bias1" sources current through R17, and Q6's base is at the voltage setpoint (filter output) + 2 * diode Vf (D3 & D4). One of these diodes roughly compensates for the Vbe voltage drop in Q10, and the other for the Vbe voltage drop in Q6. Therefore, Q6 acts like an emitter follower with its emitter voltage set to about the voltage setpoint from the op-amp & filter.
- Q6's emitter behaves as a constant-voltage "virtual ground" summing point for a voltage amplification loop (like an op-amp's inverting input), formed by R8, R2, R2c, Q4, and R7. Q6's emitter is fixed at the setpoint voltage, as just described. R8 sinks current from this summing point, while R2 either sources or sinks a current into the summing point depending on the output voltage (this is just like the feedback resistor in an op-amp gain circuit). R2c connects to the summing point of the negative output driver, and either sources or sinks current depending on the relative levels of the two summing points. Any excess current from the sum of these various currents is then conducted through Q6's collector, and drives a current mirror (roughly 57:1, based on the resistor ratios) built from Q4. The current mirror's output provides base current for Q1 and the Vbe multiplier, but more importantly creates a voltage drop across R7, which therefore sets the output voltage for the class-AB driver. In this way, the "error current" through Q6 is amplified and used to control the output voltage, creating a negative feedback loop.
- If the output voltage decreases, to keep the sum of summing-point currents equal to zero, more current must flow through Q6. This increased Q6 current is mirrored and creates a larger voltage drop across R7, increasing the output voltage again and completing the feedback loop.
- At this point, it's important to point out that the negative output driver's summing point is fixed at 0V, with D3b. R2c, linking the two output drivers' summing nodes, is responsible for forcing the complementary output voltages. When the voltage setpoint (from the filter) increases, the positive driver's summing point voltage follows it upwards as discussed earlier. This puts a larger voltage across R2c, and sources more current into the negative driver's summing point. To balance this extra current, the negative driver must decrease its output voltage, to increase the current sunk through its own R2b by an equal amount. This is what creates the "balanced" output voltages, without directly feeding a copy of the setpoint to the negative output driver.
Here's the equivalent circuit made from op-amps, if that makes it easier to understand:
[attachimg=4]
Let me know if any parts of the explanation don't make sense.
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Op-amp of some kind (2 copies)
(https://live.staticflickr.com/65535/55052862321_5f1b313ed2_z.jpg) (https://flic.kr/p/2rSQiXp)
Looks like Harris complementary bipolar process and the chip is somewhat similar to this one (https://www.eevblog.com/forum/projects/opamps-die-pictures/msg4211914/#msg4211914), which I thought was a rebadged HA-2520 (https://www.renesas.com/en/products/ha-2520), curiously still "active" at Renesas after 50 years or so. Yours may be some internally compensated variant of that.
Dunno if it's the cheapest way of receiving a differential digital signal.
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MIL-STD-1553 Transceivers, Part 2: Marconi CT3231-M-FP
(Found on this board (https://www.eevblog.com/forum/projects/avionics-teardown-engine-controller-boards/msg6143931/#msg6143931))
You can see the identical form factor of these modules, at bottom-left and bottom-right, to the previous one:
(https://live.staticflickr.com/65535/55007913252_128ef9b219_z.jpg) (https://flic.kr/p/2rNRWas)
However, the some of the differences are obvious upon opening:
(https://live.staticflickr.com/65535/55008799086_f19a2eafb9_z.jpg) (https://flic.kr/p/2rNWtus)
(https://live.staticflickr.com/65535/55007913122_c29dc1d5b1_z.jpg) (https://flic.kr/p/2rNRW8d)
Here's a 2nd look at the previous National Hybrid module, to show how much more complicated it is:
(https://live.staticflickr.com/65535/55053209020_fbfe233e03_z.jpg) (https://flic.kr/p/2rSS61Y)
The Marconi module only has a single layer of conductors (with occasional wirebond jumpers), while the National Hybrid module has at least 2 layers of conductors. The dark blue color is an insulating layer that separates the two layers. So at a minimum, the hybrid module itself is simpler & cheaper to manufacture with the Marconi one, needing fewer process steps.
How do they get away with a design that's so much simpler? The answer lies in the ICs. There's only 3 of them - the smallest is a simple, off-the-shelf 74LSR00 quad NAND gate:
(https://live.staticflickr.com/65535/55008833546_215f8e2d72_z.jpg) (https://flic.kr/p/2rNWDJA)
...but the other two seem custom. One is marked "CT11":
(https://live.staticflickr.com/65535/55007947692_d9ec658c6f_z.jpg) (https://flic.kr/p/2rNS7pf)
...and the other is marked "CT12":
(https://live.staticflickr.com/65535/55008833601_c6e5eb4761_z.jpg) (https://flic.kr/p/2rNWDKx)
They both also contain the text "MCE". This likely stands for "Micro Circuit Engineering", a British company which seems to have been mostly active in the 70's-90's (can't find any trace of them now). The "MCE" name pops up occasionally on various mostly-UK avionics I've seen.
Here's the schematic of the receive section:
[attachimg=1]
The connections from U1's input pins 2 & 3 strongly suggest that there's an op-amp inside in a classic difference amplifier configuration. R15 & R16 are the voltage divider on the non-inverting input, and R17 & R19 are the input & feedback resistors for the inverting input. The rest of the connected components (R20-R22, C8-C10) seem likely part of an EMI-and-reflections-removal filter, similar to the Sallen-Key filter on the National Hybrid module.
(I think I guessed the Q7 & Q8 connections wrong; connecting the base and collector together makes more sense than collector and emitter, putting them in an "ideal diode" configuration)
Here's the transmit section:
[attachimg=2]
Except for the biasing details of the linear output drivers, everything outside the ICs in both receive and transmit sections is pretty similar to the National Hybrid part. You can see that they've rolled all the functions of the many logic gates, op-amps, comparators, etc. and even the output-driver's discrete-transistor feedback loop from the previous module into these custom MCE ICs.
There's obviously some tradeoffs here. With custom ICs, the hybrid module itself is simpler & more reliable, with fewer wiring layers, fewer components to source/inventory/assemble, and many fewer wirebonds and solder joints (possibly the most failure-prone aspects?). However, they now have the extra time investment, cost, and inflexibility of having to design and then rely on a single source of custom ICs. The National Hybrid module could've used equivalent ICs from any number of manufacturers if they had sourcing problems - there are plenty of 74LS-series logic gates, op-amps with similar specs, TL431 equivalents, and similar comparators out there. If Marconi had problems getting their special ICs from MCE, though, it would take a whole lot of time & money (if not licensing issues too!) to take their custom design to a different IC manufacturer, have it manufactured on a new process, and the specs qualified.
In the end, neither choice is "wrong": both have their own advantages and disadvantages, and make more sense in different contexts. The same tradeoffs appear, even without custom ICs, when designing on the PCB level - do you (1) choose a special-purpose all-in-one chip that comes from one manufacturer and is irreplaceable, or do you (2) make the functions you need out of somewhat-generic building blocks (op-amps, logic gates, etc.) with only a few parts (like processors or ADCs/DACs) that don't have lots of drop-in replacements? For portable devices, you're often forced to use choice #1, just to fit size constraints - large companies also can take this approach, as they have more leverage with semiconductor manufacturers (or can buy enough chips for a full lifetime production run, so unexpected discontinuation of parts isn't an issue). For small-run or one-off R&D projects, long-lifetime designs meant to be repairable/manufacturable for decades, or for small groups or companies that are at the whims of semiconductor manufacturers and distributors, though, the second approach is usually better. The Great COVID Chip Shortage I'm sure left its mark on many engineers - the experience of watching distributor stock fluctuate wildly and having to change designs multiple times in quick succession pushed me from a slight preference for approach #2, to a "follow approach #2 absolutely whenever possible" style of design.
Anyways, hope this was an interesting look inside. If more of these pin-compatible MIL-STD-1553 transceivers turn up (from DDC, for example) I'll be taking them apart too to compare.
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Looks like Harris complementary bipolar process and the chip is somewhat similar to this one (https://www.eevblog.com/forum/projects/opamps-die-pictures/msg4211914/#msg4211914), which I thought was a rebadged HA-2520 (https://www.renesas.com/en/products/ha-2520), curiously still "active" at Renesas after 50 years or so. Yours may be some internally compensated variant of that.
Dunno if it's the cheapest way of receiving a differential digital signal.
If it was from Harris, then their complementary bipolar process used dielectric isolation, so it would have inherent enhanced radiation resistance. That by itself might be a good enough reason to use it.