Electronics > Projects, Designs, and Technical Stuff
decent but affordable 16 bit DAC
David Hess:
The tricky implementations of gain switching compensate for or are invariant of the series resistance of the switch.
https://www.analog.com/media/en/training-seminars/tutorials/MT-072.pdf
Kleinstein:
--- Quote from: nemail2 on June 09, 2019, 03:47:43 pm ---.....
My only concern is the output power needed to drive both DACs driving the opamps, especially in regards of the input voltage I'd apply to the REF5040.
The only voltage which is usable and near the REF5040 is 15V so there'd be some dissipation and warmup in the reference, if the DACs will draw the max. specified 10mA. Question is, if they will. I don't think so but I'm not 100% sure, as I didn't really have to worry about it until now.
Please have a look at my schematics, first page, upper right part: https://github.com/mamama1/LabPSU_Darlington/blob/master/schematics.pdf
Sorry for the mess, if I'd redraw it, I'd have to reroute everything as well :-(
Thanks!
--- End quote ---
The DAC8311 should not nit much more than 160 µA + the output current. The only point I see a 10 mA limit is for the output current it can deliver at some point. So the supply current should not be a problem. If heating of the reference is a problem one could consider a series resistor to drop some of the voltage. This can also work as a filter.
OM222O:
--- Quote from: David Hess on June 10, 2019, 05:20:55 am ---The tricky implementations of gain switching compensate for or are invariant of the series resistance of the switch.
https://www.analog.com/media/en/training-seminars/tutorials/MT-072.pdf
--- End quote ---
That is why I recommended different fets. Higher Rdson means lower capacitance and better transients, etc. but can introduce some errors. Higher capacitance has the opposite effect, therefore it's a tradeoff. Anyhow if the resistors are chosen to be large enough, often the Rds is orders of magnitude better than the resistor tolerance itself, making it a non issue ;D
nemail2:
Ok, so this is what I've come up with now.
i hope the digital traffic on the SPI and I2C lines won't spread to much into the analog circuitry, I've put ferrite beads in between every ADC and DAC supply line (L5, L6, L8) and I have followed datasheet instruction on bypassing and filter caps as well as I tried to follow layout recommendations.
I don't like the wasted space above the ENC pin header but I'd have to rearrange like EVERYTHING to get rid of that. Alternative would be to move the whole left part (from IC5 to the two DACs down but that would increase the trace length for current measurement (the shunt is a bit above IC13).
So basically I'm planning to go with the 4.096V voltage reference (REF5040) and with 2x DAC8311 at a fixed gain of 4 (which is even less than I have now: 6!) which will give me (nearly) zero to 16.384V output in 1mV steps.
Any objections or hints from anyone? :)
OM222O:
The parts choices seem reasonable :-+
But that layout though :-DD no offense but it seems very willy nilly without any rhyme or reason. Usually the layout follows the schematic, i.e. you have sections that do specific things, rather than just running traces all over the shop. What software are you using for the pcb design? If it's easy eda I can help you clean it up. Otherwise I can upload some pictures as hints. It would be beet to seperate your analog and digital supplies btw. LDOs are so cheap these days that there isn't an excuse for not doing so. You also won't need the ferrite beeds if you have a clean supply to start with :-/O
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