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Decoupling chips with lots of power pins

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shadewind:
I'm trying to route a board which is using a TI Stellaris MCU in a 100 pin QFP package. There are about 13 3V3 power pins and add to that 4 VDD25 power pins which take their voltage from the LDO which is built onto the chip.

My question in this is how to go about with decoupling this on a two sided board. I understand that I should have one decoupling cap per power pin which would leave me with about 17 caps which is quite a lot to fit.

If I have them on the top side, there are problems to fit anything else if I want them close to the pins. I can move them away a bit but that would make the decoupling worse I suppose (how far is too far?). Another alternative is routing most of the signals through vias in the center of the chip but is this good for signal integrity (there is, for example, an on board ethernet controller that I'll be using)? A third alternative that I've heard about people using is placing the decoupling caps on the bottom of the board right underneat the chip. What's the correct way to route using this method?

RayJones:
Seriously, any board using such high density devices should be 4 layers at the minimum.

shadewind:
Yes, probably but I'm going to try anyway. I'd rather try, fail and then learn something in the process.

The problem with cap placement would still remain if I had more layers, even if it would be a bit easier given the increased routing options.

Zad:
Perfectly do-able on 2-sided. I have used higher pin count chips than that without major problems. Sure, if it is a commercial design then you need 'enough' caps and tight impedance control, but for your own use then I wouldn't worry so much. It is not uncommon to put the caps on the groundplane layer, just try and make the via as close to the pin as you comfortably can.

mikeselectricstuff:

--- Quote from: shadewind on March 20, 2011, 07:16:48 pm ---The problem with cap placement would still remain if I had more layers, even if it would be a bit easier given the increased routing options.

--- End quote ---
Not necessarily - power planes have much lower inductance than tracks, so you can get away with fewer decoupling caps and/or you can locate them a bit further away.

As regards 2-layer routability, it's not so much about number of pins but number of different supplies, and flexibility of signal pin assignments for easy routing.
I've done 144 pin FPGAs on 2 layers & still had a decent groundplane.

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