Basic 74HC4046 PLL questions - lock range

[pitts8rh]

I have nearly zero working experience with phase locked loops, and my early attempts at putting together a simple 4046 circuit have shaken what little I thought I did understand.

The problem begins with this Maxim application circuit, described in more detail at https://www.maximintegrated.com/en/app-notes/index.mvp/id/4504 .  It supposedly covers three decades, and that is the crux of my question below :



How can a 4046 stay locked over three decades?  Or am I misunderstanding the application, and the lock range is much less with a given R1,C1 selection, and you would have to change some values to cover the full three decade range that they claim?

I understand the basic architecture above, but my questions center around basic 4046 operation, ignoring the loop counter and LPF for now.  Looking at the specs for this device, the VCO seems to have a wide range of operating frequencies depending on the choice of R1 and C1, but once those are selected it looks like the VCO range versus voltage is a lot less than I expected, like a decade at best according to the manufacturer's f_out versus VCO_in plots.

Backing off  from the more complex circuit above and prototyping a simple audio band PLL using only a single 4046 ( a TI 74HC4046 to be specific) with appropriate R1, C1 and LPF values (and without the counter in the path), I  can observe the pin 10 voltage as the loop maintains lock with varying input frequency.

What confuses me is that the lock is maintained over a much wider range than the pin 10 voltage (which I thought was just a buffered VCO_in voltage) would seem to control.  As input frequency is lowered, pin 10 voltage bottoms out, but lock is still maintained for some time.  The same happens as frequency is increased; Pin 10 voltage rises and plateaus, but lock is maintained (although degraded) well beyond that point.  Either pin 10 does not really represent the VCO voltage, or I clearly don't understand how lock is maintained.

I know this is basic stuff, but I need some help understanding what real lock range (in terms of ratio, decades, or octaves) that I could expect for a fixed R1 - C1 combination.

Thanks

[Kleinstein]

The output at pin 10 is a kind of buffered VCO signal.  AFAIR  the VCO itself uses the unbuffered signal. However this buffer might not work all the way to the rails. Especially at the lower rail, there can still be significant change in frequency without PIN 10 changing.
A range of 3 decodes is quite a lot, but still plausible, though much of the change is at the lower end of the voltage. Also not all chip might behave the same, there might be some offset at the VCO input. The locking range also depends on the loop filter.

AFAIR the value for R1 should not go so low. There is minimum value that should be higher than 100 Ohms. A relatively low value and thus high current helps to get a large range. There are also circuits using a variable current source instead of the resistor - this can give a more quadratic instead of VCO function and thus a larger useful range.

As side-note: keep an eye on the amplitude of the input signal. The sig in input does not like a signal exceeding the supply range even only a little - a smaller signal is not a problem. So if in doubt (e.g. longer cable with reflections) add a voltage-divider. 

[pitts8rh]

I am seeing quite a lot of frequency lock range both above and below the limits were the voltage on pin 10 stops moving - the VCO has to be seeing something else as you suggest.

I also questioned the low 100 ohm R1.   It seems like most references say that this should be at least 3K, with some upper limit as well.   Nevertheless, a graph of  f_out vs VCO_in on the TI data sheet shows a curve for 100 ohms R1 with a large C1 value - but I still don't see 3 decades of range there.  It's more like 10KHz to 80 Khz with .01uF C1.  Granted, the f_max/f_min ratio might be different at 64x, but I don't know that. 

Anyway, I started this all off by boldly building the circuit from the Maxim app note shown in my OP, and of course it never showed any signs of locking at any input frequency from 20 to 20,000 Hz, which led me to wonder if something was missing or off by an order of magnitude.  I've read about some of the (disturbing) variations of the PLL chip based on manufacturer, but I can't account for the total lack of success., and that's why I reverted to just a 4046 isolated on a breadboard to study its behavior. 


I'll keep an eye on the input amplitude.  I hope I haven't overdone it earlier.

[moffy]

Pin9 is the VCO input control voltage and should be what you are monitoring. Phase Comparator 2 is not only a phase comparator but also a ferquency comparator, it is that which gives the extended lock in range, but normally with a higher noise jitter on the VCO output.

[danadak]

Google "CD4046 application note", a lot of ref material out there
and how to compute lock range, capture range, etc...

Regards, Dana.

[w2aew]

My video on the very basics of Phase Locked Loops uses the CD4046.  Doesn't really get into lock range issues, but does discuss the phase detector types:

[pitts8rh]

The reason that I been monitoring pin 10 instead of pin 9 on the original circuit at higher frequency with the counter in the loop was because my scope probe was introducing noise into the LPF  (something was causing the PLL to not lock).  Somewhere I had read that pin 10 was there for the purpose of monitoring the otherwise high impedance VCO input without loading. 

And I have been using only phase comparator 2 as recommended in the original circuit for wide lock range, even though I'm not having much success.

I have Googled a bunch of app notes and several different data sheets for the 4046, and in many cases I am finding more useful tidbits of information from other manufacturers.  But I'm still not seeing any plots of VCO range versus voltage that would give me a clue that the internal VCO can span 3 octaves solely with voltage control on a fixed R1 C1 combination.  If I can't get it to span that frequency range in open loop tests, I'm having a hard time understanding how the choice of phase comparator or LPF time constant is going to help when closing the loop.  That's why I'm wondering if I'm missing some fundamental thing about how PLLs operate (particularly when locked),  or if I'm misinterpreting what Maxim is claiming in the original schematic.  The thought had crossed my mind that they meant that the circuit may be usable over a 20Hz to 20,000 Hz range, but not without switching in some different R1 C1 values to cover that span. 

 

[Audioguru]

I did not look at the 74HC4046 but instead I read about the slower CD4046 in the Cmos Cookbook.
For the frequency lockin range to be more than 3 decades then the input must be a perfect squarewave, not skinny or fat sync pulses.

[John Heath]

The reason that I been monitoring pin 10 instead of pin 9 on the original circuit at higher frequency with the counter in the loop was because my scope probe was introducing noise into the LPF  (something was causing the PLL to not lock).  Somewhere I had read that pin 10 was there for the purpose of monitoring the otherwise high impedance VCO input without loading. 

And I have been using only phase comparator 2 as recommended in the original circuit for wide lock range, even though I'm not having much success.

I have Googled a bunch of app notes and several different data sheets for the 4046, and in many cases I am finding more useful tidbits of information from other manufacturers.  But I'm still not seeing any plots of VCO range versus voltage that would give me a clue that the internal VCO can span 3 octaves solely with voltage control on a fixed R1 C1 combination.  If I can't get it to span that frequency range in open loop tests, I'm having a hard time understanding how the choice of phase comparator or LPF time constant is going to help when closing the loop.  That's why I'm wondering if I'm missing some fundamental thing about how PLLs operate (particularly when locked),  or if I'm misinterpreting what Maxim is claiming in the original schematic.  The thought had crossed my mind that they meant that the circuit may be usable over a 20Hz to 20,000 Hz range, but not without switching in some different R1 C1 values to cover that span.

I am having fun playing with the same IC 74hc4046.Forget about the max297. Its only purpose is to turn a square wave into a sine wave with a timed bucket brigade ,,, blah blah blah. The heart of it is the 74hc4046. I found it easier to separate the VCO from the phase detectors. If the target frequency is known then use two 10 k resisters from 5 volts to ground to force the VCO input to 2.5 volts. this way you can set the constant current sources to ramp up and down at the desired frequency for center control voltage of mid 2.5 volts. Now that this is set it is just a matter of phase detector 1 or 2. Phase detector 1 is just a XOR gate so symmetry in important. By symmetry I mean a square wave with 50 % duty cycle . Failing this run with phase detector 2 as it will divide by 2 returning symmetry. As an earlier poster said phase 1 is less susceptible to noise but phase detector 2 will not lock on 1/3 1/4 harmonic. It is a balancing act of what is best for a particular application. I have a nice example of 60 Hz being multiplied by 1024 for oscilloscope sync that you could find useful as a starting point to play with the 74hc4046 and a inside gate picture of the 4046. Have fun with it.

[pitts8rh]

I can't forget about the MAX297, because I need that sine wave output - key to my application. See below...

To respond to an earlier suggestion, I looked at the CD4046 and didn't see anything immediately exciting. However, I did find this comment at http://www.diystompboxes.com/smfforum/index.php?topic=54424.50;wap2 :

Quote

The CD4046 is unusual for PLLs in general in that it has
(a) a VERY wide range VCO. The VCO in the 4046 can run through a 1000:1 range.
(b) a VERY wide lock range when used with the internal phase comparator 2. The capture and lock range are essentially equal to the VCO range with PC2. PC2 is not your normal phase comparator. It is a frequency discriminator for frequency differences which are sufficiently big, so that above X frequency difference, it stays solidly high or low, forcing maximum slewing rate on the loop filter. Once within a smaller difference, it converts over to PWMing on the filter to get an analog lock. It is ... um, what was that? adaptive? by its very nature. The PC 1 on the 4046 is essentially useless for audio purposes.

This still leaves me wondering if they are talking about a wide lock range or just the range of the VCO over all R1 and C1 combinations.  When I was first looking at the 4046 in I saw the 3 decade frequency curves for various R1 values without noting immediately that they were plotted against C1 values, not voltage.

The input is not a problem - I have a clean 50% duty square wave from 0 to about 7 kHz.  Ideally I would like to turn that into a sine wave at least down to 20Hz or lower yet, and I don't know enough about PLLs to know if this is trivial or naive. I also want to be able to double and halve the input frequency, which is why I like the PLL/counter approach.  Other than the original Maxim app, I haven't come across a circuit that claims this kind of span over an audio range.

[moffy]

With R2 O/C the VCO goes from 0Hz up to fmax which in this case is slightly greater than 1.2MHz (820pf + 100R). You get more than your 3 decade range. From the app note you don't have to change filter components, but I will say that such a circuit is noise sensitive, i.e. PSU and layout sensitive, don't expect it to work on one of those plug in boards. Decouple all your IC's and provide solid supply traces. If your scope is introducing noise when probing pin 9 use a 10k resistor in series with it.

[pitts8rh]

With R2 O/C the VCO goes from 0Hz up to fmax which in this case is slightly greater than 1.2MHz (820pf + 100R). You get more than your 3 decade range. From the app note you don't have to change filter components, but I will say that such a circuit is noise sensitive, i.e. PSU and layout sensitive, don't expect it to work on one of those plug in boards. Decouple all your IC's and provide solid supply traces. If your scope is introducing noise when probing pin 9 use a 10k resistor in series with it.

Not sure what R2 O/C means, but can I assume that R2 is not used since it sets a minimum frequency?  Also, is there a plot or something that I am overlooking in the data sheets that would tell me that the internal VCO can do this 0 to f_max range?  I'm either losing it in the weeds or misinterpreting what I'm staring at.  My open loop test of the VCO range at both the 64x frequency range with the above values and at the base audio range never was able to go to 0Hz.  The lowest frequency that I was able to achieve, again open loop, for any combination of values from the audio range up to the the 64x audio range (820pf + 100R) was roughly only a decade below the f_max, and then the VCO would just stop, which seemed to agree with how I interpreted the f_out vs VCO_in   curves that I was referring to on the TI data sheet. 

BTW, the layout could very well be an issue.  It was a tight layout on a soldered universal board, and  I tried to pay attention to the grounds, PS decoupling, and current returns, particularly in the 64x path. But it didn't work, so I did something wrong.  And for what it's worth, these were TI 4046, if that makes a difference.

Have you looked at small DDS chips? For example

Funny you mention that - I think that's the direction I'm headed.  I've been looking into DDS today, which would have the extra benefit of allowing me to play with the wavetables instead of being stuck with the pure sinusoid.  I'm a little concerned about latency approaching 0Hz though, since I have to emulate the input frequency and not just pick my own.

[moffy]

O/C means Open Circuit. Refer to page 6 of Fairchild MM74HC4046 data sheet top left hand corner: Freq vs Vin for VCO with C=0.01u and R1=100, R2 open, the graph shows the frequency going from 0 to 95kHz. Page 8 top left shows the same thing. If you are not getting that then you are doing something wrong.

[pitts8rh]

Refer to page 6 of Fairchild MM74HC4046 data sheet top left hand corner: Freq vs Vin for VCO with C=0.01u and R1=100, R2 open, the graph shows the frequency going from 0 to 95kHz

Okay, that is the essentially the same curve I was looking at on the TI datasheet.  I guess I was wrongly considering only the linear region, which in hindsight makes zero sense.  I can see that it clearly is capable of operating at a much lower frequency than I was seeing on my board, although I'll have to take your word on the behavior down to zero. And when you start including 0Hz, all of a sudden the number of decades of VCO range starts looking a whole lot better (like infinite!).

I'm probably abandoning the PLL approach for this project, although I'm not letting it go completely until I can prove to myself that a stupidly simple circuit of one IC and two components can be made to oscillate open loop over the range specified.  This quick little side experiment to evaluate the Maxim PLL/Counter/LPF circuit for my audio application took on a life of its own, and it turns out that there is a better way to accomplish what is needed.

Thanks to everyone that offered guidance.

[moffy]

"I'll have to take your word on the behavior down to zero. And when you start including 0Hz, all of a sudden the number of decades of VCO range starts looking a whole lot better (like infinite!)."

It's not my word, it is what the data sheet shows. But from a logical perspective, no voltage in means no current, means no charge/discharge through the oscillator cap, means 0Hz or very close to that(leakage currents).