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Design of SMPS - Not sure what these spikes are being caused by.

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Zog:
Oh... I see your point.
All the parts he has marked as optional are in the circuit.
The inductor is a torroid.
By the way, the "different inductor" I mentioned in the above post is not a different value .. just a different Imax and Isat .. better in both, same value 4.7uH.
That's it. No other changes.

GerryBags:
This document shows some of the parasitic effects that SMPS can be subject to, my hunch is that is the diode recovery time letting through a spike before charge is drained from the p-n junction.

http://www.ee.bgu.ac.il/~smps/slides/4/DCDC_5_triple.pdf

Here's a pdf from ON about diode reverse recovery time and the effects it can have. Apparently it is a common reason that switchers fail EMI tests:

https://www.fairchildsemi.com/technical-articles/Understanding-Diode-Reverse-Recovery-and-Its-Effect-on-Switching-Losses.pdf

And for the most readable take on the subject ever, here is the classic Jim Williams app-note SMPS for poets, where he covers ways of taking measurements on them:

http://www.analog.com/media/en/technical-documentation/application-notes/an25fa.pdf

Zog:
Thanks GerryBags for the links.

I had a very quick look through and will study them properly later but they look interesting, though I know most of the stuff already. NOT an expert .. but enough to get by.

After reading those I would really like a oscilloscope current probe but can't afford a proper factory one.
I was reading somewhere else that you can home brew these from ferite beads. Anyone know of a site where I can find more information ?

Re: your hunch on the diode recovery time.

Here is the relevent specification from the datasheet for the US2GA. The supply is "supposed" to be operating at around 50kHz ... so this diode should be fast enough ?



Could that also be why the square wave at the gate is the shape it is in this shot ?



T3sl4co1l:
The schematic is fine if the voltage doubler is not used.

Absolutely no accommodation has been made to interface to a voltage doubler, and it should not be used(!).

A doubler is incompatible with a peak current mode supply, at least for any reasonable output current.  Instead, use a tapped inductor (transistor switches the tap, supply to one end, diode to the other, "long" end), so that the flyback voltage is higher than what the transistor sees.

Layout:
The connectors being in different locations ensures that, if there is ground loop voltage, it is present between them.

The ground plane is not solid, having a huge slot alongside C16, and is open under L1 and L2.  (There is no need or desire to open ground under an inductor.)  This puts a fraction of the inductor voltage around those open areas, so there will be ground loop voltage present.

The biggest problem is trusting small, high voltage electrolytic capacitors for output filtering, which they're terrible at.  Film caps would do better there, and you'll still need a bit of LC filtering to deal with the spikes that are let through by cap ESL.

As long as the controller and regs are fine with the environment, all you really should need to do, as far as spikes, is bring out all the inputs and outputs to a common ground plane, and add LC filters.  Not much L is needed.  Use ceramic chip caps (low ESL).

Tim

Zog:
Thanks for the information Tim,
Points noted on the layout.
And makes perfect sense!

I will modify the board with the ground plane recommendations you have made.

The C16 slot is just to isolate the low voltage from the HV according to the designer. Which makes sense to me.
I would imagine that it also separates the HV and LV side ground planes which is good right ?

Now.. off to search for a torroid with a tap, If such an animal exists in the wild. Somehow I doubt it.
EDIT: ... 2 toroids in series... DOH  :palm:

Hi Ho, Hi Ho it's off to Digikey I go  :)

P.S. I really appreciate all you fella's putting your 2 cent's in to this.

EDIT: not quite sure what you mean about how to arrange the circuit.

--- Quote ---A doubler is incompatible with a peak current mode supply, at least for any reasonable output current.  Instead, use a tapped inductor (transistor switches the tap, supply to one end, diode to the other, "long" end), so that the flyback voltage is higher than what the transistor sees.

--- End quote ---


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