Author Topic: Design of SMPS - Not sure what these spikes are being caused by.  (Read 5515 times)

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Online T3sl4co1l

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #100 on: September 01, 2019, 01:36:48 pm »
Looks like it's sitting pretty deep in cutoff, when unloaded.  Which makes it take a long time to throttle up.  Try putting some preload on it, like a resistor or CCS of 10% of nominal load.

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Offline Zog

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #101 on: September 01, 2019, 01:46:35 pm »
Thanks Tim,
Just mucking around with spice at the moment. Trying different ideas and different inputs to see how to drive spice, but I will do just that and post my results as usual.  :-+

edit:
I did just want to see just how hard I could hammer it too.
Nixie tubes are not that fussy about voltage spikes in the output. (to a point of course)
« Last Edit: September 01, 2019, 01:50:20 pm by Zog »
 

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #102 on: September 17, 2019, 01:59:02 pm »
Quick question guys.
I am getting in pretty deep with LTSpice now and was wondering what K coupling factor I should put in if I use two seperate inductors connected with a very short wide trace at the switch node ?
I kinda figure it won't make a lot of difference if they are really close right ?

Another one is putting in the values for the inductors ? At the moment they are just set at their nominated series resistances. Does putting peak current in make much of a difference or parallel ? I am guessing not much unless you are getting really nitty gritty and working with very complex inductor arrangements and not just my 2 effectively in series ?
 

Online MagicSmoker

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #103 on: September 17, 2019, 02:20:17 pm »
Quick question guys.
I am getting in pretty deep with LTSpice now and was wondering what K coupling factor I should put in if I use two seperate inductors connected with a very short wide trace at the switch node ?

Is this a dual boost or tapped boost? I kinda forgot which direction you ended up going here. At any rate, if a dual (probably best to say cascaded) boost then there is no coupling between the boost chokes; if a tapped boost then "it depends" noting that the leakage factor is approximately 1-(K2). So, for example, if K=0.9975 then leakage factor will be 0.005 (or 0.5%). This is typical for a single layer tapped-winding on a toroid.

Another one is putting in the values for the inductors ? At the moment they are just set at their nominated series resistances. Does putting peak current in make much of a difference or parallel ? I am guessing not much unless you are getting really nitty gritty and working with very complex inductor arrangements and not just my 2 effectively in series ?

??? Not sure what you are asking about here...

EDIT - I guess you are talking about the "secondary" parameters for the inductances? I advise specifying a realistic value for the series resistance but leave all the other stuff alone for now.
 
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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #104 on: September 18, 2019, 04:05:55 am »
Thanks for clearing that up Magic,
Tapped is what I am going for but only for the reason that they mention that - in general - flybacks are only good for 50W and forward converters are good for 150W. I read it somewhere can't remember where.
I have been getting good results from treez Dual Boost 12V to 220V at 100W_TAPPEDBUCK_CONST FREQ_1 though the part count is kinda high.

So me .. being me and and wanting to push the boundaries of just what I could do found this chip LT3757A https://www.analog.com/media/en/technical-documentation/data-sheets/3757afe.pdf.
What a little beast. One resistor for setting the clock. Wow.
I have made about 5 or so different versions of flyback and tapped boost but can come no where near the circuit treez gave to the group.

The problem I am having with the dang thing is that it will NOT keep the fet on long enough to get the inductor "saturated".
I have tried all sorts of things.

Frequency has no effect no matter how fast or slow you run the thing.
Different inductor ratios.
And on and on. Been at it for days and I don't think this thing will do it.

Pity, as is has a nice low input voltage of 2.9V up to 40V.
I have attached my latest version. Have not bothered with snubbers or gate control. Have tried all that and has no effect because the Fet just will not stay on long enough.

Is there a way I could MAKE is stay on longer. Is that even the problem ?

Happy snaps of my abomination in action.


Nice if you like rainbows. The Red trace is the Gate.


edit:
This part of the datasheet is kinda, maybe a clue ?
VC Current Mode Gain (∆VVC /∆VSENSE) 5.5 V/V
VC Source Current VFBX = 0V, VC = 1.5V –15 µA
VC Sink Current VFBX = 1.7V
VFBX = –0.85V

Or maybe a cap on the gate to lengthen the pulse somehow ? Zero clue on how I would do that though. Duty Cycle does not seem to be an option.

Edit: Again.
I think I have found my problem. Apart from the fact I can't read a data sheet properly.
Looks like it's already at almost 100% DC.

Quote
For a boost converter operating in CCM, the duty cycle
of the main switch can be calculated based on the output
voltage (VOUT) and the input voltage (VIN). The maximum
duty cycle (DMAX) occurs when the converter has the
minimum input voltage:
DMAX =
VOUT − VIN(MIN)
VOUT

More editing.
I changed the inductor ratio to 1:3.
But would you be happy with this waveform ? I mean what on earth is causing this constant ringing in the inductors ?









« Last Edit: September 18, 2019, 06:58:35 am by Zog »
 

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #105 on: September 18, 2019, 09:52:05 am »
There's 2 mistakes: change the K to K1 (for the first set of coupled inductors; K2 for the second set; etc.), and change the RC filter on the current sense line to something like 100R and 220p because you generally want the time constant of the RC filter to be in the range of 0.5x to 2x the turn-on rise time of the switch.

EDIT - by not specifying K correctly the inductors weren't coupled, so you had a boost converter feeding into an LC filter and they really don't like that. Hence the ringing. In fact, in the real world the switch would be destroyed after the first switching cycle.

EDIT 2 - I did not check the rest of your circuit.
« Last Edit: September 18, 2019, 09:54:14 am by MagicSmoker »
 
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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #106 on: September 18, 2019, 10:33:48 am »
They are 2 separate inductors so the K1 trick did not work but putting K1 L1 L2 0 ie: not coupled produced this ! Like magic  :-+
Still singing a little on L2 though. But wayyy better.

Once again I have to thank you guys for helping me out here. It's actually more enjoyable learning this now than I thought it would be. Just a few LTSpice wrinkles to iron out. Like you can't use M for megohm apparently ?
Onwards and upwards I will be doing tank circuits soon .... yer right.


 

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #107 on: September 18, 2019, 11:15:59 am »
They are 2 separate inductors so the K1 trick did not work but putting K1 L1 L2 0 ie: not coupled produced this ! Like magic  :-+
Still singing a little on L2 though. But wayyy better.

Wait, whut?! The circuit in post 104 shows what should be a tapped boost, and in such the windings must be coupled tightly for it to work. You cannot take the output of the first boost inductor and have it feed directly into another (separate) inductor or the switch will be destroyed. So you really should have something like K1 L1 L2 0.995 (or 0.9975, which gives 1% and 0.5% leakage, respectively).

Like you can't use M for megohm apparently ?

Yep, one of the quirks of LTSpice and in defiance of almost everything else is that you have to use Meg to specify a million of something; M and m are interchangeably treated as milli, or a thousandth of something.
 
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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #108 on: September 18, 2019, 11:28:38 am »
This post ?
https://www.eevblog.com/forum/projects/design-of-smps-not-sure-what-these-spikes-are-being-caused-by/msg2696312/#msg2696312
You are right of course. I was forgetting everything I learnt about the tapped toroid I did before.
Too deep in spice and I "looks" like it is working so I throw the brain out.
To self, repeat after me. I need a transformer .... I need a transformer. :palm:

Well K1 did not produce any difference. That would of course explain my sudden output voltage drop.
 

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #109 on: September 18, 2019, 02:36:54 pm »
...
To self, repeat after me. I need a transformer .... I need a transformer. :palm:

Well K1 did not produce any difference. That would of course explain my sudden output voltage drop.

So, there's a number of things wrong with 5.asc above which I have cleaned up and attached here as 5a.asc. It's not a complete design - this is my job and you ain't paying me, after all - but it should get you much closer to your (wacky) goal of powering a hundred Nixie tubes or whatever daft adventure you've set out yourself.

Note that I changed the following things:

1) Deleted extraneous specs from the input and output capacitors; first get a design working, then go back and add in ripple current and voltage ratings if you like (always include ESR, however, even if it's just a guess).

2) Added a gate resistor - always, always, always use a gate resistor when driving MOSFETs and IGBTs.

3) Changed the values on the RC filter for the current sense signal - note that this IC has a very low current sense threshold of 0.11V which makes filtering noise and spikes out of it even more critical.

4) Added an RC damper across the switch - you always need this with a tapped boost (or any configuration that has leakage inductance) - to eliminate much of the ringing. I did not optimize these values, but my guesses usually aren't too far off the mark. Usually you start with a C value that is twice the switch output capacitance then select R to be somewhere between 0.5x and 2x the characteristic impedance of the resonant network between the total capacitance and total stray inductance. Given that these parameters are sometime difficult to know ahead of time some guessing is inevitably involved. Note, also, that if the ratio of L1 to L2 is much different than 1:1 that it will become neccessary to use separate RC dampers across each inductor, rather than a single one across the switch, because the leakage inductances will be too different for one RC network to effectively damp.

5) Changed the transient simulation parameters - note that if you have to skip initial operating point in LTSpice to get a circuit to simulate, especially with one of their IC models, then something is probably wrong. It usually helps to specify the maximum timestep, however; something in the range of 0.1x to 0.5x the switching period usually ensures LTSpice doesn't inadvertently skip over ringing and other such phenomena.

6) Changed the feedback resistors to something more sensible which still gives Vout = 200V.

7) Changed the K1, L1 and L2 values to something more realistic for 300kHz CCM operation. Note that L2 has 3x as many turns as L1, so its inductance is 9x higher (inductance is proportional to turns squared). It wouldn't be unreasonable to go up to as high as 6x L1 for L2, though damping the ringing will become progressively more difficult as the turns ratio of the tapped boost increases farther away from 1:1.

8) Changed the output rectifier to the 600V SiC Schottky; this isn't strictly necessary, but sometimes a recalcitrant HV boost will behave better with this diode (as long as the average output current is <1A).

I didn't touch compensation though that almost certainly needs to be changed, and there are still some glitches in the MOSFET switching (doubled then skipped pulses - usually the result of noise on the current sense signal, though that looks pretty good at this point).
 
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Offline Zog

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #110 on: September 19, 2019, 09:39:19 am »
Quote
this is my job and you ain't paying me, after all - but it should get you much closer to your (wacky) goal of powering a hundred Nixie tubes or whatever daft adventure you've set out yourself.

No I am not paying you. But steady on now. "wacky, daft"? . Probably to some, but this project will bring me closer to world domination ! :box:
I am not really offended. You are right it is wacky and daft but I do have a serious plan for this.
Anyhoo... with that out of the way. Sniff sniff wipes tears away from eyes. :'(

Thank you for getting the thing in better shape. I still see that "ringing" in the waveforms but since it has passed your muster I guess it's acceptable "ringing". Possibly just an artifact of LTSpice ?

Quote
Usually you start with a C value that is twice the switch output capacitance then select R to be somewhere between 0.5x and 2x the characteristic impedance of the resonant network between the total capacitance and total stray inductance.

Gotcha, sorta. Thank you for that pointer. The C value is the easy part. The rest is experience and track layout but can always be tweaked later. I suspect you need very expensive equipment to do that properly though.

Quote
2) Added a gate resistor - always, always, always use a gate resistor when driving MOSFETs and IGBTs.
I swear to the SMPS gods that I will always add a gate resistor. Even if it's 1m \$\Omega\$. If I don't, may they take my first born, if they can suffer him. (kidding love the bugga).

Quote
5) Changed the transient simulation parameters - note that if you have to skip initial operating point in LTSpice to get a circuit to simulate, especially with one of their IC models, then something is probably wrong. It usually helps to specify the maximum timestep, however; something in the range of 0.1x to 0.5x the switching period usually ensures LTSpice doesn't inadvertently skip over ringing and other such phenomena.

I don't know why I use the skip the initial operating point. It worked either way but won't in future. Thank you for that tip about specifying the max timestep I had not even considered that and I will do that too in future.

Quote
7) Changed the K1, L1 and L2 values to something more realistic for 300kHz CCM operation. Note that L2 has 3x as many turns as L1, so its inductance is 9x higher (inductance is proportional to turns squared). It wouldn't be unreasonable to go up to as high as 6x L1 for L2, though damping the ringing will become progressively more difficult as the turns ratio of the tapped boost increases farther away from 1:1.

Yes get all confused about turns ratios being turns squared and larnt all I know from this video. But too thick to actually apply it in practice. :palm:

https://www.analog.com/en/education/education-library/videos/5579254291001.html

I am having a lot of trouble with magnetics in general. I mean the theory I learnt decades ago, but it still confuses me all the time. Getting old. (59).

I have been having more brainstorms. That are in the wacky category for sure.
Could one use a current transformer ? Probably not not closely coupled enough and huge leakage (guessing). But just thinking out loud here.
https://www.digikey.com/product-detail/en/pulse-electronics-power/PE-68383NL/PE-68383NL-ND/2265791
I like it because it's a tiny little bugger.

Moving on.
A proper transformer like this one.
https://media.digikey.com/pdf/Data%20Sheets/Wurth%20Electronics%20PDFs/750031353.pdf
Nice size, and probably what I should be hunting down.

Got hold of one of these from CoilCraft and this has got me stumped.
https://au.mouser.com/datasheet/2/597/da2032-463371.pdf


What sorcery is this. Each individual primary measures 10uH as per my LCR meter modified with kelvin clips at 100kHz. It's a good one not a piece of rubbish.
https://www.ebay.com.au/itm/DER-EE-DE-5000-High-Accuracy-Handheld-LCR-Meter-From-Japan-F-S/202765545258?hash=item2f35c4af2a:g:AAYAAOSwG-1ZxKJ0

Ok, fair enough but you can then put 3 of them in parallel and it still says 10uH ?. I did and it does. What ? wait ... err.. inductors in parallel are supposed to act like resistors. Not so according to the CoilCraft magnet gods.

Well if that's true. I am getting hold of a bunch of these to play with. I think these are the magic beans that will help me actually get a bit of flexibility so I don't have to remake a board every time.

https://www.coilcraft.com/pdfs/hexa-path.pdf
« Last Edit: September 19, 2019, 09:45:59 am by Zog »
 

Online MagicSmoker

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #111 on: September 19, 2019, 11:22:35 am »
...
Thank you for getting the thing in better shape. I still see that "ringing" in the waveforms but since it has passed your muster I guess it's acceptable "ringing". Possibly just an artifact of LTSpice ?

No, the ringing is still a problem; I just got it better, not perfect. Tweaking the values of the snubber and even filtering the current sense signal more will be warranted, but I needed to leave some work for you to do, eh? Also, using a smaller FET (ie - higher on resistance/lower current rating) would help, as it will have a smaller output capacitance (Cjo in LTSpice).

That said, you're never going to eliminate all ringing in a hard-switched (that is, non-resonant) converter... Not without seriously degrading efficiency, anyway. And LTSpice does a really good job of getting such behavior correct - better than some professional SPICE packages with prices in the 5 digit range - so no, the ringing isn't just an artififact of the program, it really will occur (now, whether the ringing occurs at the exact frequency and amplitude depends on how accurate you were at determining all of the stray Ls and Cs).

Gotcha, sorta. Thank you for that pointer. The C value is the easy part. The rest is experience and track layout but can always be tweaked later. I suspect you need very expensive equipment to do that properly though.

Some empirical testing will likely be required, regardless, so just plan on trying a few different capacitor values on the prototype board. Snubber values are rarely critical (as evidenced by the frequent use of suspiciously generic values like 100pF + 10k or 10nF + 10R [seem familiar?], etc.)

I swear to the SMPS gods that I will always add a gate resistor. Even if it's 1m \$\Omega\$. If I don't, may they take my first born, if they can suffer him. (kidding love the bugga).

There are two reasons for the gate resistor: 1) it limits peak current charging/discharging the gate capacitance; 2) it suppresses ringing between that capacitance and stray wiring inductance.

Could one use a current transformer ? Probably not not closely coupled enough and huge leakage (guessing).

For measuring current, sure, though usually not worth the expense until the peak current is at least 10A or so and the sense signal is scaled to 1V peak.

Otherwise, yes, a proper transformer for L1/L2 would be better, but note that you can get pretty good results with a commercially available toroid with the right L2 value then adding the 1/3rd to 1/6th turns required for L1 on top of it as that will likely get leakage down into the 0.5% to 1% range. It's hard to do that well with any of the E cores (ETD, EFD, ER, EER, EC, etc.), actually.

EDIT  - forgot to add that the reason paralleled windings on a common core don't decrease in inductance is because they are all tightly coupled together. It's really no different than if the winding was made of multiple strands of insulated wire if you think about it. For the inductance to decrease in parallel - as happens with resistors - then you need the windings to be on separate cores with no interaction between them (that is, little to no mutual inductance).
« Last Edit: September 19, 2019, 11:24:42 am by MagicSmoker »
 

Offline Zog

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #112 on: September 19, 2019, 01:36:03 pm »
Quote
EDIT  - forgot to add that the reason paralleled windings on a common core don't decrease in inductance is because they are all tightly coupled together. It's really no different than if the winding was made of multiple strands of insulated wire if you think about it. For the inductance to decrease in parallel - as happens with resistors - then you need the windings to be on separate cores with no interaction between them (that is, little to no mutual inductance).

Ohhh. Ok thanks for clearing that up I thought the laws of physics had been changed while I was on the toilet.

Just going through cores on digikey.
This mob seem to have a material at the right sort of frequency so should not get too hot from core losses right ? https://www.ferroxcube.com/upload/media/product/file/MDS/3f3.pdf at least compared to plain old ferrite ?
I really would like a nice cool end result. As cool as possible anyway.

Digikey have this thing available.
https://www.digikey.com.au/products/en/magnetics-transformer-inductor-components/ferrite-cores/936?k=&pkeyword=&sv=1&v=1779&pv70=1069&sf=0&FV=1d480002%2C1f140000%2Cffe003a8&quantity=&ColumnSort=0&page=1&nstock=1&pageSize=500
Looks like it might be a bugger to wind though.
And they indicate inductance factor of 4.5uH So that is the max I will get out of it ?

I looked here but got a little lost.
http://www.encyclopedia-magnetica.com/doku.php/al_value

« Last Edit: September 19, 2019, 01:38:21 pm by Zog »
 

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #113 on: September 19, 2019, 04:31:32 pm »
AL is inductance per turn squared. If it says 4.5uH then a single turn will have an inductance of 4.5uH, 2 turns = 18uH, 3 turns = 40.5uH, etc.

Ferroxcube 3F3 (and TDK/EPCOS N87) are both excellent ferrites for 300kHz operation.

I ain't reviewing random cores, okay, but the pot core you pulled up is just about the worst choice possible, really.

Instead, look at part number 2100LL-180-H-RC on DigiKey which is an 18uH toroidal choke rated for 10.1A saturation current using a relatively low-loss material (Sendust). You could use the existing winding as the primary then wind on top of it, say, 4x as many turns, tying the start of the new winding to the end of the existing one to make a 1:4 autotransformer. Et voilla, a semi-custom tapped inductor for about $4 and a few minutes of your time. It will likely run hot and you'll have to restrict the peak current well below the claimed 10.1A saturation rating (maybe 5-6A peak), but it will be good enough to get something working and teach you a bit in the process.


 

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #114 on: September 20, 2019, 02:37:49 am »
Quote
AL is inductance per turn squared. If it says 4.5uH then a single turn will have an inductance of 4.5uH, 2 turns = 18uH, 3 turns = 40.5uH, etc.
Great. That makes it easy.

Yes I am already using a "fairydust" core. They still run a bit hot for my liking but will play around with it some more till I get the inductance right then proceed to order a super pixie dust toroidal.

I have enough information now to ask my CoilCraft rep what he can do for me I think.
 

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #115 on: September 21, 2019, 10:30:50 am »
Something is still bugging me.
All the datasheets mention Irms for their current ratings and not peak to peak.
Surely I should be following that advice and not be using peak to peak for inductor selection ? Right ?
 

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #116 on: September 21, 2019, 10:32:14 am »
Irms is a thermal rating only.

You're looking for saturation current, which should be greater or equal to the peak current used in circuit.

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #117 on: September 21, 2019, 10:34:02 am »
Ok. That's two of you now telling me. I will listen. Thank you. :-+

edit: one more quick question.
A 10uH to 1000uH is a 1:10 ratio right. I just need you guys to tell me that I am not a complete idiot.
« Last Edit: September 21, 2019, 10:43:40 am by Zog »
 

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #118 on: September 21, 2019, 11:08:20 am »
Ok. That's two of you now telling me. I will listen. Thank you. :-+

edit: one more quick question.
A 10uH to 1000uH is a 1:10 ratio right. I just need you guys to tell me that I am not a complete idiot.

And you better pay close attention to the inductance at "rated saturation current" as it has typically fallen to 50% of the unbiased value, which is way lower than the usual definition of when "saturation" occurs (that is, by anyone besides commercial choke manufacturers), or a decline of 20% to, at most, 30%. Hence why I said you might want to limit peak current in a commercial choke to 50% of the saturation rating.

And yes, if one winding is 10uH and the other winding is 1000uH (1mH) then the turns ratio is 10 (either 1:10 or 10:1, depending on the direction).

EDIT - and no, not all the datasheets only mention RMS current; the part number I suggested before has Isat ratings, too.
« Last Edit: September 21, 2019, 11:10:33 am by MagicSmoker »
 
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Offline Zog

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #119 on: September 21, 2019, 11:34:28 am »
Great.
I realise that most mention Isat, but was a little confused.

Should I also include that huge inrush when it first starts up and getting to voltage as part of the selection process ? I am guessing yes. ie: I should take the peak to peak of the whole simulation and not just when it has settled down.

I am guessing yes because it's not working if it's saturated of course. But then again it's only for a few ms so is it that mission critical ?

edit:
Quote
as it has typically fallen to 50% of the unbiased value
better look up what that means.
« Last Edit: September 21, 2019, 11:36:03 am by Zog »
 

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #120 on: September 21, 2019, 11:51:25 am »
...
Should I also include that huge inrush when it first starts up and getting to voltage as part of the selection process ? I am guessing yes. ie: I should take the peak to peak of the whole simulation and not just when it has settled down.

Yep. Inrush causing the boost choke to saturate is a major problem at higher power levels, but at this power level simply using the controller IC's soft-start function will deal with it.

Quote
as it has typically fallen to 50% of the unbiased value

better look up what that means.

Hmmm... I didn't think that was worded ambiguously. If you look at the datasheet for any of these commercial chokes* they will both state the inductance at zero current - ie, unbiased by DC - as well as the inductance at rated current or saturation or the like. In this part number I suggested earlier the unbiased inductance is 18uH, the rated current is 10.1A, but the inductance at that current has fallen to 8.5uH, or 47% of the unbiased value. This means that the real current rating isn't anywhere close to 10.1A.

* - a note on terminology: a choke is an inductor designed to tolerate DC bias without saturation.
 
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Offline Zog

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #121 on: September 21, 2019, 12:00:54 pm »
Sorry man. It's just that I am reading so much stuff it's kinda making my head spin.
Thank you for spelling it out for me. edit: better have a very close look at those curves.

Well. I have had a crack at making a 1:10 using this
https://au.mouser.com/datasheet/2/597/da2032-463371.pdf They do in all fairness to them say it is made for capacitor charging with a different chip. But I though I would try to see how it went.
Err... ugly. It's fine at say 20mA's or so .. but boy does it not like to draw a lot of current above that.

I bought one using the above inductor off ebay. Fine up to 40mA's but errr.. yer. After I blew it up I removed all the chips off and had a good look at the layout though, so all was not wasted. Very nice.


Attached for your amusement.

« Last Edit: September 21, 2019, 12:06:48 pm by Zog »
 

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #122 on: September 21, 2019, 12:54:09 pm »
The DA2034 is a great little flyback transformer, but if that is what you are thinking of using then you might as well design a flyback rather than screw around with the tapped boost, dual/cascaded boost, etc.

Note that the dot ends of each winding in a flyback are inverted with respect to the other. E.g. - if the dot end of the primary is connected to the supply voltage then the non-dot end of the secondary goes to the output diode.

You can also use this transformer in the tapped boost by connecting the dot end of the primary to the 12V supply, the non-dot end of the primary to the dot end of the secondary, and the non-dot end of the secondary to the output rectifier. If you find the switch blowing up at a tiny fraction of expected power output then the most likely cause is that you've connected the dot end to the dot end (or the non-dot end to the non-dot end).

Also note that you need some kind of clamp across the primary to protect the switch in a flyback; the RCD type is preferred, but even a series fast diode + zener or TVS diode can work. If using the latter choose a zener/TVS voltage at least 50% higher than the reflected output voltage (which is the output voltage divided by the secondary:primary turns ratio; e.g. - 200V / (10:1) = 20V; set clamp voltage to 30V or higher).

This is probably a lot to digest, but I can't distill 20+ years of SMPS design into a few forum posts, even if you paid me.

 
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Offline Zog

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #123 on: September 21, 2019, 01:33:27 pm »
Thank you once again for your valuable tips.
I am designing a flyback at the moment with this.
https://www.coilcraft.com/pdfs/hexa-path.pdf
The flexibility is great and I am getting good results so far.
The snubber is noted. Though the application notes are a little confusing.

I am going for this one.


Not this one, if that even is a snubber.

 

Offline Zog

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #124 on: September 22, 2019, 08:07:20 am »
I think I might have something that works BUT. Now I am worried about wattages.
I should of course be using Average for this right ? Peak to peak is insane.

Another question too if I may. I am trying to get the model as close as I can and my datasheet mentions leakage and interwinding capacitance. Leakage I can do with the K factor but where do I put in the interwinding capacitance ?
In the primary or the secondary or both ?
https://au.mouser.com/datasheet/2/597/da2032-463371.pdf

P.S.
I am sure you guys know about this little magic bean. https://www.analog.com/media/en/technical-documentation/data-sheets/8304fa.pdf
200V right out of the box with no external mosfet.
Looks a little tricky to get right though and not enough amps for me. The application notes are an interesting read though all the same.

The transformer they recommend is right on the edge with the amps so I don't really know how they do it.

 


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