Author Topic: Design of SMPS - Not sure what these spikes are being caused by.  (Read 5488 times)

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Offline treez

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #25 on: May 19, 2018, 09:57:53 pm »
your mosfet you say is switching unevenly.
You can  often correct this by judicious adjustment of the current sense filter and the fet gate series resistor.
But there is no gate series resistor in your schem. I think you need one.

Sometimes of course, uneven fet switching can be caused by insufficient slope compensation in current mode designs.
Sometimes it can be caused by insufiicient delta current in the current signal, ie you have used too big inductance and the on state current ramp is so shallow that it easily hits the sense threshold through noise instead of in the normal way.

Also, here is my pcb layout doc attached

Oh by the way, a  lot of the spikes i saw are just "pickup"...induced into the scope probes impedance by all the noise that an smps chucks out.
There is a test to see if it is pickup....connect your  scope ground clip to the probe tip  and see if you see the spikes still, with the probe tip touching whichever node on the circuit.
« Last Edit: May 19, 2018, 10:01:58 pm by treez »
 
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Offline Zog

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #26 on: May 19, 2018, 11:45:57 pm »
Ok.. thanks for clarifying.
Rather than spending lots of money on more parts I am going to try centre taping my existing torroid and arranging it into the circuit as is without any other changes and see what sort of results I get.
You mentioned an inverter transformer. But have never said which one .. did you ?
« Last Edit: May 20, 2018, 05:54:13 am by Zog »
 

Offline T3sl4co1l

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Offline Zog

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #28 on: May 20, 2018, 12:30:33 am »
Gotcha,
Thanks.
It's of significant orders of magnitude larger in L... 1.2mH @ 65kHz ....
Would that make much of a difference generally speaking ?
The original design runs the minimum recommended by TI, 50kHz.

Oh.. by the way ... what does SRF or LPD mean ? not Self Resonant Frequency surely ?

Quote
*Glances back at the OP*, oh yeah, a couple amps will be needed, won't it.  Well, most of these are families, should be able to find something bigger SRF or LPD or whatever.  Or that inverter transformer is looking quite good, despite its size and cost. :)

 

Offline T3sl4co1l

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #29 on: May 20, 2018, 12:47:48 am »
Gotcha,
Thanks.
It's of significant orders of magnitude larger in L... 1.2mH @ 65kHz ....
Would that make much of a difference generally speaking ?
The original design runs the minimum recommended by TI, 50kHz.

I said run it backwards.  If it's 10:1, then the "secondary" is 1000 times less or 12uH.  Right in the ballpark. ;)

Quote
Oh.. by the way ... what does SRF or LPD mean ? not Self Resonant Frequency surely ?

Self resonant frequency, yes, but I was referring to the part families.

Tim
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Offline Zog

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #30 on: May 20, 2018, 12:50:31 am »
Gotcha,
Well worth the 5 bucks I paid !  ;) cough  ;D
Cheers Mate.
« Last Edit: May 20, 2018, 01:49:36 am by Zog »
 

Offline Zog

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #31 on: May 20, 2018, 01:00:30 am »
your mosfet you say is switching unevenly.
You can  often correct this by judicious adjustment of the current sense filter and the fet gate series resistor.
But there is no gate series resistor in your schem. I think you need one.

Sometimes of course, uneven fet switching can be caused by insufficient slope compensation in current mode designs.
Sometimes it can be caused by insufiicient delta current in the current signal, ie you have used too big inductance and the on state current ramp is so shallow that it easily hits the sense threshold through noise instead of in the normal way.

Also, here is my pcb layout doc attached

Oh by the way, a  lot of the spikes i saw are just "pickup"...induced into the scope probes impedance by all the noise that an smps chucks out.
There is a test to see if it is pickup....connect your  scope ground clip to the probe tip  and see if you see the spikes still, with the probe tip touching whichever node on the circuit.


Thanks very much for your input treez very much appreceated mate. Thank you for taking the time to share that write up.
I "know" some of that but your tip on how on connecting the scope ground clip to the probe tip and probing around is one I would never of thought of.
Thanks again  :-+

P.S. You didn't do all that writing just for this topic did you ? or was it something you had already done ?
« Last Edit: May 20, 2018, 01:10:28 am by Zog »
 

Offline Zog

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #32 on: May 20, 2018, 05:39:12 am »
Question for anyone who knows about 1:10 ratio coupled inductors.
If the primary turn has an inductance of 25uH what would be the inductance of the secondary ?

The usual way is to do this right ?
M2 = L1+L2
M2=Mutual Inductance

But the datasheet does not supply L2 Only L1

Sooo .. I am guessing that the datasheet is just showing the total mutual inductance and there is no way to work it out.  Even using the ratio ? (btw I am not great at maths  :P)

« Last Edit: May 20, 2018, 06:10:17 am by Zog »
 

Offline T3sl4co1l

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #33 on: May 20, 2018, 07:22:23 am »
Datasheets never give M, it's a rather useless figure, it arises from physics but you never measure it in circuit.

Hmm, well I suppose you can, since the definition is:
Vp = Lp * dIp/dt (single inductor, Vp = primary voltage, Ip = primary current)
Vs = M * dIp/dt (coupled inductor, Vs = secondary EMF, Ip = primary current)
You'd apply a constant AC current to the primary, and measure the secondary current.  M drops out from the secondary, while Lp drops out from the primary (and if you apply the current to the secondary, you measure Ls instead).

Anyway, you're more likely to measure Lp, Ls and k (coupling factor).  https://en.wikipedia.org/wiki/Leakage_inductance
LL is easily measured by shorting one winding and measuring the other winding inductance.  LL, k, and M (as a product of Lp, Ls) are all easily related.

Since they don't give any of k, M or LL, it's impossible to know them, or Ls exactly.  Presumably, Ls is around (10/1)^2 * Lp, or 2500uH.

Incidentally, you use the inductance ratios in SPICE, not the turns ratio.  So to model this, you need to enter the inductances accordingly, and put in a coupling statement ("K12 L1 L2 0.98", say).

Tim
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Offline Zog

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #34 on: May 20, 2018, 10:25:56 am »
Thanks for the explaination Tim,

Ok back to the chase.

Edit: Here is a pretty picture of how I tapped the torroid.



This is a better drawing of the circuit with the test points marked.
Edit: yes I know that it does not show the original input caps as per the original circuit ... but they are there. I have just been working on a different input circuit so have not shown them on this sheet.



First point to note. Is I can only get a maximum of 85mA's out now. Not the 140mA I was getting before.
Only thing changed is I have center tapped the torroid as shown above.

Second point. As the shot below shows I am now not missing any gate pulses. So the tap is working ? I guess.
Still a lot of ringing but no snubber yet so that is expected.

Taken at TP2 at only 35mA


Following Shots Taken at TP3 at 85mA



Zoomed in a little



Close up



Hoping that the rest of the snubbers will fix this.

BUT .. why the lower max mA's out ?












« Last Edit: May 20, 2018, 11:02:39 am by Zog »
 

Offline b_force

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #35 on: May 20, 2018, 10:43:57 am »
Still missing a snubber in this circuit.
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Offline Zog

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #36 on: May 20, 2018, 10:47:33 am »
I think I mentioned that  :)
The original one is there C11 and R7.
« Last Edit: May 20, 2018, 10:54:30 am by Zog »
 

Offline b_force

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #37 on: May 20, 2018, 11:12:03 am »
I think I mentioned that  :)
The original one is there C11 and R7.
I am talking about a snubber across the MOSFET.
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Offline Zog

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #38 on: May 20, 2018, 11:13:38 am »
Of course.
Please read back a few pages.
It has been mentioned  :)
Indeed it has even been drawn !  :)

Edit: this is the droid you are looking for master skywalker
https://www.eevblog.com/forum/projects/design-of-smps-not-sure-what-these-spikes-are-being-caused-by/msg1550420/#msg1550420

P.S. do you have any clues as to why a center tap would reduce the amps out ?   ;D
« Last Edit: May 20, 2018, 11:19:11 am by Zog »
 

Offline b_force

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #39 on: May 20, 2018, 11:50:56 am »
Of course.
Please read back a few pages.
It has been mentioned  :)
Indeed it has even been drawn !  :)

Edit: this is the droid you are looking for master skywalker
https://www.eevblog.com/forum/projects/design-of-smps-not-sure-what-these-spikes-are-being-caused-by/msg1550420/#msg1550420

P.S. do you have any clues as to why a center tap would reduce the amps out ?   ;D
Ok, my apologies.
It's not showing in the schematic in your last post, so that's a little confusing ;)

With the center tap probably something has to do with halving the inductance maybe
With a center tap I would suggest using a higher value.
« Last Edit: May 20, 2018, 12:44:39 pm by b_force »
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Offline Zog

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #40 on: May 20, 2018, 11:55:59 am »
No probs "brah"  :)
Thanks for the clue !
Cheers,
Phill from W.A.
 

Offline b_force

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #41 on: May 20, 2018, 12:48:48 pm »
No probs "brah"  :)
Thanks for the clue !
Cheers,
Phill from W.A.
You can simulate these kind of things pretty easy btw.
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Offline Zog

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #42 on: May 20, 2018, 01:35:32 pm »
Yes.. I have tried in TI workbench.
But no result.
Spice is probably better but how many trees must I chop down to see the forest ?
 

Offline T3sl4co1l

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #43 on: May 20, 2018, 03:01:13 pm »
Building a representative model in a simulator does take some knowledge of the simulator itself, and trust in the models (or preferably, verification -- and knowing how to do that).

The ringing you are seeing is common mode, there's no reason for that signal to be on that pin as such (it has a capacitor to ground across it!).  That's just ringing you will probe literally anywhere in the circuit -- because it's actually voltage drop across the probe's ground lead!

Reducing drain rise time will address that.  Hence the RCD rate subber I drew. :)

Output current: probably lower because primary inductance is lower?  A 50% tap gives Lp ~= 25% of total inductance.  Maximum peak current remains the same, so you get less energy per cycle = less average power.  Ideally what you'd have done: wind the same (or more) number of turns on top. :)

Tim
« Last Edit: May 20, 2018, 03:04:26 pm by T3sl4co1l »
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Offline Zog

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #44 on: May 20, 2018, 06:38:38 pm »
Yes of course ... 1/4 the inductance not 1/2 I see now.
Will get winding.

I have a very nice LCR meter with kelvin clips .. so should be able to get a good job done.

Which ringing are you talking about ?
The one on test point 2 or 3 ?
 

Offline b_force

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #45 on: May 20, 2018, 06:42:22 pm »
Output current: probably lower because primary inductance is lower?  A 50% tap gives Lp ~= 25% of total inductance.  Maximum peak current remains the same, so you get less energy per cycle = less average power.  Ideally what you'd have done: wind the same (or more) number of turns on top. :)

Tim
That's the part you can simulate.
Just cut your model down, and change the value of the inductor and see what it does.

The ringing is a different story, although there are guidelines to figure where to look.
Just google on it, so many great articles and papers about it.
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Offline Zog

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #46 on: May 20, 2018, 06:54:18 pm »
You are right. Many great articles on it.
Trouble is you can't ask an article a question.

Hence why this forum is what it is.
A great way for people to help each other out about the things they don't understand just by reading them.

No need for teachers if we could all just read it in a book right ?

The "just google it" seems to be a catchall these days. It's good but not always the best way to get the exact knowledge you seek.
I am sure you agree. I have seen some of your posts  ;)
« Last Edit: May 20, 2018, 06:56:34 pm by Zog »
 

Offline b_force

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #47 on: May 20, 2018, 07:00:52 pm »
You are right. Many great articles on it.
Trouble is you can't ask an article a question.

Hence why this forum is what it is.
A great way for people to help each other out about the things they don't understand just by reading them.

No need for teachers if we could all just read it in a book right ?

The "just google it" seems to be a catchall these days. It's good but not always the best way to get the exact knowledge you seek.
I am sure you agree. I have seen some of your posts  ;)
Yes I agree, and I don't often say it, but in this case I do believe there are some papers out there that will explain and summarize much better than I can.  8)
"If you can't explain it simply (or at all), you don't understand it well enough." A. Einstein

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Offline Zog

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #48 on: May 20, 2018, 07:02:42 pm »
Indeed ,and if you had followed the thread from the start, you would see that someone has already provided what I think is one of the best ones out there in this very thread !
« Last Edit: May 20, 2018, 07:10:43 pm by Zog »
 

Offline b_force

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #49 on: May 20, 2018, 07:22:57 pm »
Indeed ,and if you had followed the thread from the start, you would see that someone has already provided what I think is one of the best ones out there in this very thread !
I don't really follow what you're referring to.
I did read the thread, but haven't seen a solution yet?

Anyway, doesn't matter.
The point is, with switching supplies a lot comes down to the PCB design and which parts you choose as well.
I will dive into my pile of papers later do show a better understanding of it  ;) :)
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