Electronics > Projects, Designs, and Technical Stuff

Design of SMPS - Not sure what these spikes are being caused by.

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Zog:
No probs "brah"  :)
Thanks for the clue !
Cheers,
Phill from W.A.

b_force:

--- Quote from: Zog on May 20, 2018, 11:55:59 am ---No probs "brah"  :)
Thanks for the clue !
Cheers,
Phill from W.A.

--- End quote ---
You can simulate these kind of things pretty easy btw.

Zog:
Yes.. I have tried in TI workbench.
But no result.
Spice is probably better but how many trees must I chop down to see the forest ?

T3sl4co1l:
Building a representative model in a simulator does take some knowledge of the simulator itself, and trust in the models (or preferably, verification -- and knowing how to do that).

The ringing you are seeing is common mode, there's no reason for that signal to be on that pin as such (it has a capacitor to ground across it!).  That's just ringing you will probe literally anywhere in the circuit -- because it's actually voltage drop across the probe's ground lead!

Reducing drain rise time will address that.  Hence the RCD rate subber I drew. :)

Output current: probably lower because primary inductance is lower?  A 50% tap gives Lp ~= 25% of total inductance.  Maximum peak current remains the same, so you get less energy per cycle = less average power.  Ideally what you'd have done: wind the same (or more) number of turns on top. :)

Tim

Zog:
Yes of course ... 1/4 the inductance not 1/2 I see now.
Will get winding.

I have a very nice LCR meter with kelvin clips .. so should be able to get a good job done.

Which ringing are you talking about ?
The one on test point 2 or 3 ?

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