Author Topic: Design of SMPS - Not sure what these spikes are being caused by.  (Read 5475 times)

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Offline treez

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #75 on: August 23, 2019, 09:30:57 pm »
Quote
I don't have a preference for input voltage.  Looking at a mean well supply…

OK so I take   it your power source will be an offtheshelf power supply from eg meanwell.
You could get the LRS-150-48….
https://www.meanwell.com/webapp/product/search.aspx?prod=LRS-150
This has a 48V output.
Then you  just need to boost up from 48V to your 185V, 100W output.
 
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Offline Zog

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #76 on: August 24, 2019, 03:43:12 am »
Thanks treez,
The biggest problem at the moment is layout.
You mentioned you have an eaglecad 7x version.
Is it possible to export my version 9x back to eagle 7x for you to have a look at ?
 

Offline treez

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #77 on: August 24, 2019, 08:26:45 am »
Hi,
Yes i can try and open it in my eagle here. Ill have a look, yes.
 
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Offline treez

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #78 on: August 24, 2019, 10:18:27 pm »
Hi Zog,
As was discussed, your  vin = 12v, vout = 220v and pout = 100w. Your chosen  topology is the tapped boost.

One problem  for the tapped boost with such high “primary” current  (around 14A peak in your case) is that unless you can ensure very tight coupling between the two sections of the tapped inductor, then you are going to get high voltage spikes on the drain of the fet whenever it turns off. I think you may  need  (depending on your actual coupling) to put a clamp across the primary side of the tapped inductor as in the attached. The bare  basic schematic is attached…also the LTspice simulation. This is a free  download  simulator and you will find it very easy to use.
Just  open the simulation (.asc file)  and hit the running man icon….then click away at your leisure to see the circuit voltages and currents…ALT, Left click to see the power…….its a lot easier than that TI webbench one.
 Its always best to run some kind of representative simulation of a SMPS first before going to the bench. If an SMPS works on the simulator, then it doesn’t mean it will work on the bench, but generally, if you cant get some kind of representative simulation working first, then its  often  a waste of time going to the bench. All the best SMPS engineers ive worked with  at places like Alcatel, Tridonic, etc etc are avid users of simulators…….if only just to check over what you are about to do on the bench.
I think  a tapped boost inductor at the current levels here, would  preferably need to be interleave wound to increase coupling….otherwise I suppose you can just have a chunky clamp resistor and just eat up the leakage energy like that.
Your vin is only 12v, and your peak fet current is going to be in the region of 14A or so…….so you will need a fet with low rds(on)….but also, if you are getting high voltage drain spikes  due to the leakage inductance, then you will need the fet to be rated to that high voltage….the problem is that low rds(on) fets are often not available with high voltage ratings.

Anyway, if you dont use a fet with low enough rds(on), then you are just not going to get enough power throughput, as the volt drop in a high rds(on) would mean your effective input voltage is even lower than 12v.......this would get worse as the fet warms up and its rds(on) increases.
One of your schems shown here shows a fet with 3 ohms rds(on), and thats the min value.....you wont be able to get much current through that from a 12v input.

This is one  of the reasons doing a sim first is good.,...it flags up points like that which are so easy to forget.

This is why I believe that the Dual Boost converter is better for you, and I have provided  details in a following post. In the Dual boost converter…the   fet that sees the higher current only sees a low voltage, and so you can easily find suitable fets. Also, the Dual Boost doesn’t have coupled coils, so leakage inductance does not have to be dealt with.
Leakage inductance isn’t too bad when not much current flows in it…because the energy of the leakage inductance is i^2.R. But with your high-ish peak current, you could end up with high leakage energy to dissipate….depending on how well coupled are your coils.
Even with a tapped boost, the high step up ratio is likely to mean that you will need slope compensation. If you  pick a constant off time controller then you won’t need to use slope compensation.
« Last Edit: August 24, 2019, 10:43:47 pm by treez »
 
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Offline treez

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #79 on: August 24, 2019, 10:28:07 pm »
I think for vin=12v, vout = 220v, pout = 100w, you are better  off with the dual Boost converter as  in the attached….

....either using constant frequency operation, or constant off time (COT) …….const freq needs slope compensation, COT does not.
The dual boost is very good because the fet that sees the higher current sees a lower voltage, so you can easily find low rds(on) ones. This is important for you since your vin is so low……any volt drop in the rds(on) will subtract from the input voltage and make it even  lower. The Dual boost only uses one controller as shown. LTspice simulation also attached. It just uses simple inductors..no coupling required.
 
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Offline treez

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #80 on: August 24, 2019, 10:30:15 pm »
LTspice quick start guide attached if you need it....you easily have the knowledge to be able to run a LTspice sim and view the circuit voltages and currents.
If you   want to run it, just open the .asc file and hit the running man icon....when youve finished, delete the large .wav file or  else your hard disk will eventually  fill up if you keep running different sims.
« Last Edit: August 24, 2019, 10:32:15 pm by treez »
 
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Offline Zog

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #81 on: August 25, 2019, 12:04:48 am »
HOLY HAND GRENADE BATMAN ! ;D ;D ;D

You my friend, are a true legend and not just in your own underpants !

You have been busy haven't you.

Time to have another crack at LTSpice.

I don't quite know how to thank you for this. A forum thanks does not seem adequate.

But THANKS ! :-+ :-+

I will of course keep you posted on how I go with this.

P.S. early versions of eagle will not open later versions as far as I know.

edit:
Mate I am loving this LTSpice !
Your quick start guide and the circuits you have supplied have made it so easy now to adjust component values.
I have been thinking of making the rsense divider network adjustable using a trim pot for example.
Now I just have to change the values to see what range I can adjust it to and look at the wave forms.
TI Workbench is rubbish compared to this.
Thank you so much for suggesting the UCC28C43 as a replacement too. It's datasheet layout guide is so much easier to understand that the chip I was using for the other design.

I have a few more questions if I may impose on you again.
Why would I use the constant frequency over the over the constant off time circuits. Does one have any advantages over the other ?
I don't see much difference in the output ?

Constant time off (no slope compensation)


Constant frequency (slope compensation)




The tapped boost is confusing me too. How would I get the pulse into the mosfet ? (custom pulse circuit ?)

« Last Edit: August 25, 2019, 06:08:14 am by Zog »
 

Offline treez

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #82 on: August 25, 2019, 09:59:29 am »
Quote
Why would I use the constant frequency over the over the constant off time circuits. Does one have any advantages over the other ? I don't see much difference in the output ?

Yes in this case it doesn’t matter too much…COT is more helpful when there is a wide range of Vin (or wide range of vout)…COT means that  in cases of wide vin range, the  increase of duty cycle wont be as unmanageable as with a constant frequency converter….typically, as duty cycle increases, the off-time gets less with a const freq converter, and sometimes there is a limit to how low the off time can get…so if you have a COT converter……well, your off time is fixed to an acceptable level in the first place, so its never going to get ridiculously small…….however, it does mean that your switching frequency changes as the vin changes……with COT you have to examine all conditions of load and line to tell that your switching frequency never gets too ridiculously high.
Another point is that COT converters don’t ever need slope compensation…….which means you don’t have to  bother with that.

Another point is that there's not many COT pwm controllers on the market off the shelf....the LT1248 that i show  in the sim is a const freq converter that i hacked in the sim to work in COT.
The HV9910B is another COT chip
Onsemi do one also.
But there arent many others.

The Tapped Boost is attached here in LTspice sim.......it takes ages to run unfortunately.....and if you put in the leakage inductance by going "K L1 L1 0.99", it then takes even longer.
There arent FETs in LTspice with high enough voltage and low enough rdson........so i have to make a behavioural source and just drive loads of high rdson fets in parallel...(like i did in the previous  abbreviated tapped boost sim)
With the tapped boost attached here, if you add in the leakage inductance , the fet then  gets overvoltaged.....by the leakage spikes....so then you have to change to a 600v fet.....but then its rdson is  too high....so you then have to  go adding more in parallel ...and then of course theres too much  gate capacitance for the pwm chip to drive...so you then have to add a behavioural source to  mimic the pwm controller output.
« Last Edit: August 25, 2019, 10:15:14 am by treez »
 
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Online T3sl4co1l

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #83 on: August 25, 2019, 10:23:52 am »
Note the downside to constant-time and hysteretic converters: the ripple is all over the place, especially at the operating extremes.  At high frequency, switching loss is more significant; at low frequency, reactive losses are more significant (inductor core/winding loss, filter cap ESR), and input and output voltage ripple/noise.

Controllers with reasonably well bounded frequency are easier to design filters for.  They're also easier to observe on the oscilloscope, which is probably helpful in development.

Tim
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Bringing a project to life?  Send me a message!
 

Offline treez

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #84 on: August 25, 2019, 10:49:37 am »
Oops sorry, i used the wrong diode in the tapped boost simulation, please find the corrected version here.
 

Offline treez

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #85 on: August 25, 2019, 11:06:26 am »
top of page 4 of this
http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.913.7541&rep=rep1&type=pdf

shows how you can measure your tapped inductor coupling coefficient, k.

This is important as it affects the duty cycle needed to get from vin to vout......too much leakage and your D max may not be big enough for you to get vout from vin

(woops, just realised i accidentlaly wrote "overlap" instead of "overload" in the above simulations annotation, i also accidentally called the "tapped boost" a "tapped buck" simulation...sorry about that)
« Last Edit: August 25, 2019, 01:59:27 pm by treez »
 

Offline Zog

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #86 on: August 25, 2019, 02:00:41 pm »
I am confused again.

After running your new update in LTSpice I see significant changes and was wondering what caused the changes.

The original sim had a nice slow startup from zero volts and was stable at 9ms.


Original V4


The corrected version shows this. I did turn off the Skip initial operating point solution to show it a little more clearly but is only nearly stable at 30ms.



Revised V4


I made up a little voltage divider with these values and replaced V4 in the original with it and it worked well.


What benefit is this ? I took it out and it made no obvious difference  to the output ?









« Last Edit: August 25, 2019, 02:02:43 pm by Zog »
 

Offline treez

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #87 on: August 25, 2019, 02:15:02 pm »
So you are comparing the tapped boost with one of the dual boosts.....i confess i havent bothered changing the feedback compensation components for the tapped boost...and the dynamics of the tapped boost are likely to be more  complex than the dual_boost.....so i reckon the tapped boost could be speeded up by changing the feedback compensation components......

The LTC6101 based circuit is purely for startup and  overload.........it stops the "staircasing" of the inductor cuirrent at startup which is prevalent in many smps's when they are starting up and the vout is well below what it shoudl be.,............its the vout which "discharges" the inductor so if its not  high enough you get too high currents in the power stage...therefore i put in the ltc6101 sensor and the extra error amplifier to limit the current........but it will just lie dormant when the converter has got started.

It sounds like you have hacked it to be in current limit mode all the time by reducing the 2.8volts to 0.5..........thats isnt what the current limiter is meant for.

So also you coudl try clicking the ".ic v(out) = 220v" and make that a comment instead  of a spice directive...that may speed it up.......but otherwise i think the complex dynamics of the tapped boost mean the feedback compensation components need changing to make it startup quicker and oscillate less during startup.

The little filter inductor L3, is purely to keep the current ripple out of the sense resistor of the ltc6101 current monitor...and of course, this only operates at startup (or overload)...so yes, ususally this doesnt do much...(but woudl be good for emc in a real converter)
I dare say the ltc6101 probably works well enough if L3 is omitted.
(Apologies for my fat finger typing in places.)
« Last Edit: August 25, 2019, 02:26:40 pm by treez »
 
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Offline Zog

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #88 on: August 25, 2019, 02:40:31 pm »
Thanks again treez,
I changed the V4 to a voltage divider in the Dual Boost original. Is that ok ?
 

Offline treez

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #89 on: August 25, 2019, 03:03:54 pm »
...yes as long as the voltage is the same.....it only goes into an opamp input, and as you yknow, these are very high impednace, so no problems with the divider here.....it just sets the limit that the input current is set to, so that you dont get too much current at startup...after that the error amp concerned just goes dormant.

By the way, if you like, there is my free switch mode power supply course which explains a lot about SMPS's....
https://drive.google.com/open?id=0B7aRNbu3Fes4TU92Mkw3YlA3ams

{...always interested to here if all course folders from A to Z (sorry, "Y")  got sucessfully downloaded, so please  say  if the download didnt work}

Here is also my guide to doing an electronics degree
https://massey276.wixsite.com/electronicsdegree
« Last Edit: August 25, 2019, 04:02:51 pm by treez »
 

Offline Zog

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #90 on: August 26, 2019, 06:52:17 am »
treez,
Something wrong with your latest Dual Boost ?
Only showing 210mW output ?



 

Offline Zog

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #91 on: August 28, 2019, 09:44:30 am »
I am an idiot.
No load in sim.
Just got back to working on it. shows 100W as advertised.
 

Offline Zog

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #92 on: August 29, 2019, 10:11:08 pm »
Quote
By the way, if you like, there is my free switch mode power supply course which explains a lot about SMPS's....
https://drive.google.com/open?id=0B7aRNbu3Fes4TU92Mkw3YlA3ams

WOW. So much information and a great course treez.
I was wondering on how to do so many things and having a skim through it I found many answers to my questions. Well done mate.

So many links to great resources. Spreadsheets and on and on and on. If you made it into a wiki I think you would be the number one resource for beginners like me.
I won't be asking so many questions now (I hope) that I have this little gem in my pocket.

I was wondering how to make the supply into a 25W one for instance and putting two or more in parallel to get more power if I need it and I now have the info I need.

Not found out how to lower the output to 25W yet though. But will keep digging, I am sure it's in there somewhere. Probably just mucking around in spice and selecting different components.

Layout is still my biggest hassle. I am still working on that, but there are lots of resources to calculate currents in tracks etc. So I might eventually get through that barrier.

Quote
Here is also my guide to doing an electronics degree
https://massey276.wixsite.com/electronicsdegree

At 59 it's a little late for me. Particularly as maths is not my strongest point.

Cheers treez.
« Last Edit: August 29, 2019, 10:13:17 pm by Zog »
 

Offline Zog

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #93 on: August 30, 2019, 05:22:24 am »
Did not take long.
Another question.
In spice when looking at the current through L2 should I be selecting an appropriate inductor based on Average current or RMS.
I am presuming RMS correct ?

And that current should be less than the saturation current I am guessing.

edit: stupid question. should be RMS given the wave shape.
edit2: .. err.. shouldn't it ? :scared:

More editing:
Looking at this one for L2 in the tapped buck
https://www.digikey.com.au/product-detail/en/pulse-electronics-power/PE-54036SNL/553-1419-ND/1037030
« Last Edit: August 30, 2019, 05:55:48 am by Zog »
 

Offline MagicSmoker

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #94 on: August 30, 2019, 09:42:21 am »
...
In spice when looking at the current through L2 should I be selecting an appropriate inductor based on Average current or RMS.
...

Neither: it is the peak current that is most important in selecting the inductor, as that determines the energy handling requirement. RMS current is relevant only in selecting the wire diameter.
 
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Offline Zog

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #95 on: August 31, 2019, 07:46:02 am »
Thanks for clearing that up magic.
I removed the previous post because it was a silly mistake on my part.
I figured that little problem out and didn't want to clutter up the forum.
 

Offline Zog

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #96 on: August 31, 2019, 10:51:16 pm »
Having trouble stepping the output load in LTspice

Not sure what I am doing wrong but I want to be able to step the load to see the transient analysis.
I have looked all over google and can't find a definitive answer.

I am not sure how or where to set the flagloads option to flag the external current source to be a load.


« Last Edit: August 31, 2019, 10:52:58 pm by Zog »
 

Online T3sl4co1l

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #97 on: September 01, 2019, 03:49:16 am »
Use the PULSE type.  Alternately, use some resistors, a switch and a VPULSE.

Tim
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Bringing a project to life?  Send me a message!
 
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Offline MagicSmoker

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #98 on: September 01, 2019, 10:57:32 am »
Having trouble stepping the output load in LTspice

There's a couple ways to do this, but I like to use a the voltage controlled switch model ("SW") driven by a pulse source.

You need to include a .model statement in your circuit which specifies the relevant parameters for the switch like so:

.model SW SW(Ron=1m Roff=10Meg Vt=4 Vh=-1)

And then drive it with a voltage pulse source that delivers 10V when on, has the rise and fall times you desire, etc.
 
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Offline Zog

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #99 on: September 01, 2019, 12:32:11 pm »
Thank you very much MagicSmoker and Tim,

That was a great way to do what I wanted and by providing the .model example I had it completed in 1/2 Hour.
I don't want to "bless" you all with my appalling Frankenstein of a hack just yet so will show you the bit that did the trick.



Look at that lovely disruption.  :clap:



P.S. I have to thank treez for getting me into LTSpice too. If he had not provided me with a starting point I would never have got anywhere. Everyone needs a "hello world" to get going !




« Last Edit: September 01, 2019, 12:38:57 pm by Zog »
 


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