Author Topic: Design of SMPS - Not sure what these spikes are being caused by.  (Read 5487 times)

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Offline Zog

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Hi all,
I am making a boost converter for nixie tubes and have got mine running at 185VDC at 140mA's at the moment.
Yes .. I know .. "just how many nixies are you running !" ... well none yet. I just want to see how far I can push the design.

Edit: for this circuit.




My scope is showing these spikes on the HV feedback line.





And these on the Mosfet gate.





After half an hour the vpp was also increasing from almost nothing to this.



Even at only 30mA's I still see the spikes on the feedback line.



The gate does not look so bad though.





Any clues on where I can find out more on this subject would be greatly appreciated.

Cheers,
Phill




« Last Edit: May 20, 2018, 09:55:02 am by Zog »
 

Offline Zog

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #1 on: May 14, 2018, 02:01:04 pm »
Could it be my snubber ? Perhaps ?
But what could explain the missing switching in the mosfet ?
 

Offline Tomorokoshi

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #2 on: May 14, 2018, 03:03:04 pm »
Can you post pictures of the schematic and the actual test setup?
 
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Offline rx8pilot

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #3 on: May 14, 2018, 03:37:51 pm »
The only way to have an actionable comment is to share your schematic, the physical build, and the test setup.

I would hazard a guess that most of what you see is noise from the measurement itself, the rest of it is dominated by how you built (PCB layout) the circuit. Once you have considered those two major elements, you may need a simple RC snubber to damp the ringing on the switch node.

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Offline Zog

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #4 on: May 14, 2018, 03:43:27 pm »
I am building this guys design and have used his layout.

https://jan.rychter.com/high-voltage-power-supply-for-nixie-tube-projects

The test setup is not ideal.

Will try the small clips on the probe tomorrow and try again.
Using the crocodile lead is probably making an antenna for sure.
Thanks for the reminders !
 

Offline rx8pilot

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #5 on: May 14, 2018, 04:43:36 pm »
If you don't have one of these, you can make one easy enough with solid wire and a screwdriver slightly smaller than the tip of the probe.

Also, consider using a load resistor. A no-load condition will change the characteristics of the SMPS.
Factory400 - the worlds smallest factory. https://www.youtube.com/c/Factory400
 
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Offline Zog

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #6 on: May 14, 2018, 10:23:13 pm »
Yes .. I have those for the probes.
The load is about 1.4k through a 30w adjustable wire wound ceramic resistor and a 5W ceramic resistor. Not ideal for such a huge output, and the poor old little 5 watt resistor gets so hot it melts the solder on the connection. I am truly amazed that it has not blown up yet. They are tough little buggers.
Will take a few more measurements today and report back.
Thanks for the tips.
« Last Edit: May 14, 2018, 10:26:12 pm by Zog »
 

Offline Phoenix

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #7 on: May 14, 2018, 11:31:54 pm »
Something doesn't seem right to me on those waveforms. Are you able to probe the gate and the output voltage (if safe to do so with your scope) simultaneously? Also, what does the voltage across your current measurement resistor look like?

Do you have the voltage doubler in place? If so can you try without it?

Can you attach YOUR schematic and YOUR photo?
 
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Offline Zog

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #8 on: May 15, 2018, 12:15:38 am »
Will try the measurements you suggest.
And the ones in the other post.

Yes the voltage doubler is in place.
I can remove it.

My schematic is the same as the one I linked to.
I am using testpoints 1,2 and three in that circuit.

My photo won't show you much as it's the same as his board.
Infact it IS his board ... just with a different mosfet, inductor and lower current sense resistors.
 

Offline Phoenix

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #9 on: May 15, 2018, 12:17:49 am »
The point about YOUR schematic is that he lists a lot of parts as optional. Maybe you can copy his schematic and take out the parts that are not there.
 
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Offline Zog

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #10 on: May 15, 2018, 12:39:23 am »
Oh... I see your point.
All the parts he has marked as optional are in the circuit.
The inductor is a torroid.
By the way, the "different inductor" I mentioned in the above post is not a different value .. just a different Imax and Isat .. better in both, same value 4.7uH.
That's it. No other changes.
« Last Edit: May 15, 2018, 12:43:10 am by Zog »
 

Offline GerryBags

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #11 on: May 15, 2018, 12:46:52 am »
This document shows some of the parasitic effects that SMPS can be subject to, my hunch is that is the diode recovery time letting through a spike before charge is drained from the p-n junction.

http://www.ee.bgu.ac.il/~smps/slides/4/DCDC_5_triple.pdf

Here's a pdf from ON about diode reverse recovery time and the effects it can have. Apparently it is a common reason that switchers fail EMI tests:

https://www.fairchildsemi.com/technical-articles/Understanding-Diode-Reverse-Recovery-and-Its-Effect-on-Switching-Losses.pdf

And for the most readable take on the subject ever, here is the classic Jim Williams app-note SMPS for poets, where he covers ways of taking measurements on them:

http://www.analog.com/media/en/technical-documentation/application-notes/an25fa.pdf
 
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Offline Zog

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #12 on: May 15, 2018, 01:30:10 am »
Thanks GerryBags for the links.

I had a very quick look through and will study them properly later but they look interesting, though I know most of the stuff already. NOT an expert .. but enough to get by.

After reading those I would really like a oscilloscope current probe but can't afford a proper factory one.
I was reading somewhere else that you can home brew these from ferite beads. Anyone know of a site where I can find more information ?

Re: your hunch on the diode recovery time.

Here is the relevent specification from the datasheet for the US2GA. The supply is "supposed" to be operating at around 50kHz ... so this diode should be fast enough ?



Could that also be why the square wave at the gate is the shape it is in this shot ?



 

Offline T3sl4co1l

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #13 on: May 15, 2018, 01:51:07 am »
The schematic is fine if the voltage doubler is not used.

Absolutely no accommodation has been made to interface to a voltage doubler, and it should not be used(!).

A doubler is incompatible with a peak current mode supply, at least for any reasonable output current.  Instead, use a tapped inductor (transistor switches the tap, supply to one end, diode to the other, "long" end), so that the flyback voltage is higher than what the transistor sees.

Layout:
The connectors being in different locations ensures that, if there is ground loop voltage, it is present between them.

The ground plane is not solid, having a huge slot alongside C16, and is open under L1 and L2.  (There is no need or desire to open ground under an inductor.)  This puts a fraction of the inductor voltage around those open areas, so there will be ground loop voltage present.

The biggest problem is trusting small, high voltage electrolytic capacitors for output filtering, which they're terrible at.  Film caps would do better there, and you'll still need a bit of LC filtering to deal with the spikes that are let through by cap ESL.

As long as the controller and regs are fine with the environment, all you really should need to do, as far as spikes, is bring out all the inputs and outputs to a common ground plane, and add LC filters.  Not much L is needed.  Use ceramic chip caps (low ESL).

Tim
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Offline Zog

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #14 on: May 15, 2018, 02:07:50 am »
Thanks for the information Tim,
Points noted on the layout.
And makes perfect sense!

I will modify the board with the ground plane recommendations you have made.

The C16 slot is just to isolate the low voltage from the HV according to the designer. Which makes sense to me.
I would imagine that it also separates the HV and LV side ground planes which is good right ?

Now.. off to search for a torroid with a tap, If such an animal exists in the wild. Somehow I doubt it.
EDIT: ... 2 toroids in series... DOH  :palm:

Hi Ho, Hi Ho it's off to Digikey I go  :)

P.S. I really appreciate all you fella's putting your 2 cent's in to this.

EDIT: not quite sure what you mean about how to arrange the circuit.
Quote
A doubler is incompatible with a peak current mode supply, at least for any reasonable output current.  Instead, use a tapped inductor (transistor switches the tap, supply to one end, diode to the other, "long" end), so that the flyback voltage is higher than what the transistor sees.


« Last Edit: May 15, 2018, 05:54:55 am by Zog »
 

Offline T3sl4co1l

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #15 on: May 15, 2018, 06:51:49 am »
I would imagine that it also separates the HV and LV side ground planes which is good right ?

If you're going to use slots, better to position the LV section opposite the HV area, not hugging around it.  That is, put the +12V in the middle.

Quote
Now.. off to search for a torroid with a tap, If such an animal exists in the wild. Somehow I doubt it.
EDIT: ... 2 toroids in series... DOH  :palm:

Hi Ho, Hi Ho it's off to Digikey I go  :)

Nooo, not in series, you need coupling!

Winding coils isn't hard, otherwise look for tapped inductors.  DK has 1:1 to 1:10 ratios stocked, IIRC.  Look for the same "primary" (smaller winding) inductance as the original design.  You probably won't find toroids, but there are lots of ferrite and molded SMT inductors, and inverter transformers (use the "secondary" as primary, e.g. a 120 (or 85-265) to 12V transformer would do very nicely here).

Incidentally, "torroid", is that phonetic, or is there a regional or language influence?  It's a very common typo but I'm unsure and curious why...

Quote
EDIT: not quite sure what you mean about how to arrange the circuit.
Quote
A doubler is incompatible with a peak current mode supply, at least for any reasonable output current.  Instead, use a tapped inductor (transistor switches the tap, supply to one end, diode to the other, "long" end), so that the flyback voltage is higher than what the transistor sees.

Consider what happens in the instant the transistor turns on: it draws a huge gulp of current through both doubler capacitors.  The controller detects this and shuts off the pulse short.  Result: huge EMI (hard switching, high peak currents), very low output power (low duty cycle).

Once it's up to voltage, it can be okay, because the current will be small when the capacitor voltage is very close to the peak-to-peak voltage already.  But it won't take much load to pull it down into the range where it falls over.

Whereas a tapped inductor, just works the way the circuit normally does, and you can get nearly any voltage you want. ;)

Tim
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Bringing a project to life?  Send me a message!
 
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Offline Zog

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #16 on: May 15, 2018, 07:16:54 am »
Torroid  is the shape .. so I just call them that. Most people I know do too. Toroidal is of course the correct term though, I guess .

Back to the chase.

I am replacing that LV design and putting in a better one. That one has no input protection UV or OV and I am going to need a VDD of 12VDC for the Tube HV drivers.
I have already moved it out of the way so I can do that. No board made yet until I get it this part right.

Code: [Select]
Nooo, not in series, you need coupling!Still don't get it. Coupling ? You mean I have to use a transformer ... right ?

The thing is, the way it is at the moment drawing that amount of current it gets as hot as hell.
I mean really hot. the mosfet gets to about 85c and the current sense resistors get to 80c !
The "Torroidal" inductor gets to about 50c ... but that is not on the board so that's fine.

Obviously efficiency is not ... err great  ;D

Man this thing can pump out some current though even if it's not efficient !
The 5w load resistor gets to 200c
This was all tested at 25c after only 30 minutes.
Output dropped from 140mA to 135mA after that time ... so I guess the inductor was having a hard time and was derating.

Will start looking for transformers. Though I am not really sure how I am going to wire it up.

Thanks again for your interest Tim,
Phill


 

Offline T3sl4co1l

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #17 on: May 15, 2018, 07:29:46 am »
Yes, a transformer.  Well, sort of.  A transformer that stores energy (in other words, a tapped, coupled inductor).  Not an ideal transformer (which does not store energy and has infinite inductance)! :)

Part of the problem is huge input currents and awkward duty cycles, because the circuit attempts to make a large voltage ratio between input and output.  The tapped inductor fixes this, making it a very normal (ideally 1:1.5 to 1:3 ratio) converter, as far as everything else is concerned.

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Offline Zog

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #18 on: May 15, 2018, 07:31:22 am »
Got it !  :-+
Looking on DK now
 

Offline Zog

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #19 on: May 15, 2018, 09:14:53 am »
Still looking.
The 1:1 ratio inductors will cause the same problems so they are out.

Code: [Select]
Once it's up to voltage, it can be okay, because the current will be small when the capacitor voltage is very close to the peak-to-peak voltage already.  But it won't take much load to pull it down into the range where it falls over.
Whereas a tapped inductor, just works the way the circuit normally does, and you can get nearly any voltage you want. ;)

For the same reason above I assume ?

Just checking

EDIT: ... stupid question of course it will. Just can't find one that is suitable.
Would someone please be good enough to rub my nose in one that would do the job that is reasonably small ? PCB mount SMT or through hole ?

EDIT AGAIN:... I think this is an impossible task.

For something
1. smallish
2. the right current rating
3. the right voltage rating
4. the right saturation rating
5. the right inductance.

This came close but no cigar.

https://www.digikey.com.au/products/en/transformers/switching-converter-smps-transformers/168?k=&pkeyword=&pv1393=21&FV=1f140000%2Cffe000a8%2C15c0001b%2C15c0002d%2C15c0004b%2C15d00006&quantity=0&ColumnSort=0&page=1&stock=1&nstock=1&pageSize=500

Perhaps a snubber on the switch node would be a possibility ? At least that would knock of the EMI right ?

Even More EDITING:

"For those playing along at home"  ;D


Direct link to the article. https://www.fairchildsemi.com/application-notes/AN/AN-4162.pdf


« Last Edit: May 15, 2018, 11:40:25 am by Zog »
 

Offline Zog

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #20 on: May 16, 2018, 03:44:42 pm »
Still working on this stuff fella's
Tim has got me out of the bog hole I was in.
Will update you on progress as I incorporate his ideas into the new design.
 

Offline Zog

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #21 on: May 19, 2018, 07:22:18 am »
This is part of the circuit suggestions I paid Tim (T3sl4co1l) a few bucks for his time for.

I thought I would throw it out there before committing to it.



I see what he means now.

I have a few concerns though.
None of the inductors suggested have very high current Irms(A). The Irms(A) of the torroid I am using is 10A and even that gets hot.
So the question is will the design above still need a high current coupled inductor.

The way I see it is it is still charging the 4.7uf cap and the 10uH inductor so it needs to supply the current, right ?


Will the only thing this circuit do is reduce the ringing with coupled inductor and the snubbers
If that is the case can't I just use the existing circuit and just add the snubbers ?
Edit:...belay that. I have been working on something else for a few days and have not been concentrating on the one project.


The other question I have is if I use a coupled 4.7uH 1:1 inductor why use the extra 10uH one ?

Edit: Because the suggested 1:10 inductor is only 27uH  and I will need the extra 10uH ?
If I use a 1:1 I could leave it out ?


Edit: see above. One more question is what advantages or disadvantages are gained or lost by using a ratio of 1:3 or 1:X etc ?

Little bit confusing to me.
Little less confusing to me.

Anyway Tim is obviously an expert and I very much appreciate his work, but rather than pester him with messages privately, I thought it would be better for all, to continue this search for the high power design I am looking for publicly.

Edit: I read this again.
So I "think" I get it.
Quote
Part of the problem is huge input currents and awkward duty cycles, because the circuit attempts to make a large voltage ratio between input and output.  The tapped inductor fixes this, making it a very normal (ideally 1:1.5 to 1:3 ratio) converter, as far as everything else is concerned.

More Editing:

This is the datasheet for the 6235 1:10 Ratio

Not quite the same circuit example as Tim's above though.



Sorry about the crazy editing !  :P
« Last Edit: May 20, 2018, 05:52:49 am by Zog »
 

Offline T3sl4co1l

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #22 on: May 19, 2018, 02:02:01 pm »
None of the inductors suggested have very high current Irms(A). The Irms(A) of the torroid I am using is 10A and even that gets hot.
So the question is will the design above still need a high current coupled inductor.

*Glances back at the OP*, oh yeah, a couple amps will be needed, won't it.  Well, most of these are families, should be able to find something bigger SRF or LPD or whatever.  Or that inverter transformer is looking quite good, despite its size and cost. :)

Probably most of the heat in your toroid was core loss, so that it's practically irrelevant if the winding is rated 10A or 100A.  With a waveform that peaky, you get a lot of excess heating -- another good reason to use a tapped winding or transformer. ;)

Quote
The other question I have is if I use a coupled 4.7uH 1:1 inductor why use the extra 10uH one ?

Edit: Because the suggested 1:10 inductor is only 27uH  and I will need the extra 10uH ?
If I use a 1:1 I could leave it out ?

What extra 10?

Inductance depends on operating frequency and desired current ripple.  4.7uH might be enough, or you may need to raise the frequency, or deal with the higher ripple (increased losses, especially in the inductor and main filter caps).

I was looking for values near the original primary inductance, but I didn't check if that was consistent with the controller's operating point.  The datasheets for those controllers are very detailed, do take a look and double-check the original author's work. :)

Quote
This is the datasheet for the 6265 1:10 Ratio

Not quite the same circuit example as Tim's above though.



That's an interesting one.  Must be... self-excited oscillator, for single-cell battery or solar or thermopile or energy harvesting purposes?  So, the capacitors are there to help shift charge around, without having to put too many different windings on the poor little transformer.  Something like that.  It's not a good method to use at scale; you can get away with it at low voltages because, with so little voltage to begin with, you're going to get crap efficiency anyway (anything over 50% is good), and since you're only doing this for a couple watts at most, the parts are small and you can afford to overkill them a bit, so they'll tolerate hacks like turn-on switching into a capacitor load.

Notice the current path from MOSFET drain, through the transformer, coupling cap, sync rect, and output filter, back to ground.  When the transistor turns on, it delivers a huge gulp of current to charge that capacitor, which means big switching losses.

Tim
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Offline Zog

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #23 on: May 19, 2018, 03:03:32 pm »
Thanks for the reply Tim.
I am off to bed ... will analyse your answers after a good snooze.
Marked the 10uH inductor on the hand drawn circuit.
P.S. What inverter transformer ?
« Last Edit: May 19, 2018, 03:15:00 pm by Zog »
 

Offline T3sl4co1l

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #24 on: May 19, 2018, 03:36:08 pm »
Oh yeah, just for extra filtering (same thing that appears on the other sheet).  You'll still want it regardless of switching inductor value, because current is going into and out of the circuit in pulses.

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Offline treez

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #25 on: May 19, 2018, 09:57:53 pm »
your mosfet you say is switching unevenly.
You can  often correct this by judicious adjustment of the current sense filter and the fet gate series resistor.
But there is no gate series resistor in your schem. I think you need one.

Sometimes of course, uneven fet switching can be caused by insufficient slope compensation in current mode designs.
Sometimes it can be caused by insufiicient delta current in the current signal, ie you have used too big inductance and the on state current ramp is so shallow that it easily hits the sense threshold through noise instead of in the normal way.

Also, here is my pcb layout doc attached

Oh by the way, a  lot of the spikes i saw are just "pickup"...induced into the scope probes impedance by all the noise that an smps chucks out.
There is a test to see if it is pickup....connect your  scope ground clip to the probe tip  and see if you see the spikes still, with the probe tip touching whichever node on the circuit.
« Last Edit: May 19, 2018, 10:01:58 pm by treez »
 
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Offline Zog

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #26 on: May 19, 2018, 11:45:57 pm »
Ok.. thanks for clarifying.
Rather than spending lots of money on more parts I am going to try centre taping my existing torroid and arranging it into the circuit as is without any other changes and see what sort of results I get.
You mentioned an inverter transformer. But have never said which one .. did you ?
« Last Edit: May 20, 2018, 05:54:13 am by Zog »
 

Offline T3sl4co1l

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Offline Zog

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #28 on: May 20, 2018, 12:30:33 am »
Gotcha,
Thanks.
It's of significant orders of magnitude larger in L... 1.2mH @ 65kHz ....
Would that make much of a difference generally speaking ?
The original design runs the minimum recommended by TI, 50kHz.

Oh.. by the way ... what does SRF or LPD mean ? not Self Resonant Frequency surely ?

Quote
*Glances back at the OP*, oh yeah, a couple amps will be needed, won't it.  Well, most of these are families, should be able to find something bigger SRF or LPD or whatever.  Or that inverter transformer is looking quite good, despite its size and cost. :)

 

Offline T3sl4co1l

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #29 on: May 20, 2018, 12:47:48 am »
Gotcha,
Thanks.
It's of significant orders of magnitude larger in L... 1.2mH @ 65kHz ....
Would that make much of a difference generally speaking ?
The original design runs the minimum recommended by TI, 50kHz.

I said run it backwards.  If it's 10:1, then the "secondary" is 1000 times less or 12uH.  Right in the ballpark. ;)

Quote
Oh.. by the way ... what does SRF or LPD mean ? not Self Resonant Frequency surely ?

Self resonant frequency, yes, but I was referring to the part families.

Tim
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Offline Zog

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #30 on: May 20, 2018, 12:50:31 am »
Gotcha,
Well worth the 5 bucks I paid !  ;) cough  ;D
Cheers Mate.
« Last Edit: May 20, 2018, 01:49:36 am by Zog »
 

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #31 on: May 20, 2018, 01:00:30 am »
your mosfet you say is switching unevenly.
You can  often correct this by judicious adjustment of the current sense filter and the fet gate series resistor.
But there is no gate series resistor in your schem. I think you need one.

Sometimes of course, uneven fet switching can be caused by insufficient slope compensation in current mode designs.
Sometimes it can be caused by insufiicient delta current in the current signal, ie you have used too big inductance and the on state current ramp is so shallow that it easily hits the sense threshold through noise instead of in the normal way.

Also, here is my pcb layout doc attached

Oh by the way, a  lot of the spikes i saw are just "pickup"...induced into the scope probes impedance by all the noise that an smps chucks out.
There is a test to see if it is pickup....connect your  scope ground clip to the probe tip  and see if you see the spikes still, with the probe tip touching whichever node on the circuit.


Thanks very much for your input treez very much appreceated mate. Thank you for taking the time to share that write up.
I "know" some of that but your tip on how on connecting the scope ground clip to the probe tip and probing around is one I would never of thought of.
Thanks again  :-+

P.S. You didn't do all that writing just for this topic did you ? or was it something you had already done ?
« Last Edit: May 20, 2018, 01:10:28 am by Zog »
 

Offline Zog

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #32 on: May 20, 2018, 05:39:12 am »
Question for anyone who knows about 1:10 ratio coupled inductors.
If the primary turn has an inductance of 25uH what would be the inductance of the secondary ?

The usual way is to do this right ?
M2 = L1+L2
M2=Mutual Inductance

But the datasheet does not supply L2 Only L1

Sooo .. I am guessing that the datasheet is just showing the total mutual inductance and there is no way to work it out.  Even using the ratio ? (btw I am not great at maths  :P)

« Last Edit: May 20, 2018, 06:10:17 am by Zog »
 

Offline T3sl4co1l

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #33 on: May 20, 2018, 07:22:23 am »
Datasheets never give M, it's a rather useless figure, it arises from physics but you never measure it in circuit.

Hmm, well I suppose you can, since the definition is:
Vp = Lp * dIp/dt (single inductor, Vp = primary voltage, Ip = primary current)
Vs = M * dIp/dt (coupled inductor, Vs = secondary EMF, Ip = primary current)
You'd apply a constant AC current to the primary, and measure the secondary current.  M drops out from the secondary, while Lp drops out from the primary (and if you apply the current to the secondary, you measure Ls instead).

Anyway, you're more likely to measure Lp, Ls and k (coupling factor).  https://en.wikipedia.org/wiki/Leakage_inductance
LL is easily measured by shorting one winding and measuring the other winding inductance.  LL, k, and M (as a product of Lp, Ls) are all easily related.

Since they don't give any of k, M or LL, it's impossible to know them, or Ls exactly.  Presumably, Ls is around (10/1)^2 * Lp, or 2500uH.

Incidentally, you use the inductance ratios in SPICE, not the turns ratio.  So to model this, you need to enter the inductances accordingly, and put in a coupling statement ("K12 L1 L2 0.98", say).

Tim
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Offline Zog

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #34 on: May 20, 2018, 10:25:56 am »
Thanks for the explaination Tim,

Ok back to the chase.

Edit: Here is a pretty picture of how I tapped the torroid.



This is a better drawing of the circuit with the test points marked.
Edit: yes I know that it does not show the original input caps as per the original circuit ... but they are there. I have just been working on a different input circuit so have not shown them on this sheet.



First point to note. Is I can only get a maximum of 85mA's out now. Not the 140mA I was getting before.
Only thing changed is I have center tapped the torroid as shown above.

Second point. As the shot below shows I am now not missing any gate pulses. So the tap is working ? I guess.
Still a lot of ringing but no snubber yet so that is expected.

Taken at TP2 at only 35mA


Following Shots Taken at TP3 at 85mA



Zoomed in a little



Close up



Hoping that the rest of the snubbers will fix this.

BUT .. why the lower max mA's out ?












« Last Edit: May 20, 2018, 11:02:39 am by Zog »
 

Offline b_force

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #35 on: May 20, 2018, 10:43:57 am »
Still missing a snubber in this circuit.
"If you can't explain it simply (or at all), you don't understand it well enough." A. Einstein

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Offline Zog

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #36 on: May 20, 2018, 10:47:33 am »
I think I mentioned that  :)
The original one is there C11 and R7.
« Last Edit: May 20, 2018, 10:54:30 am by Zog »
 

Offline b_force

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #37 on: May 20, 2018, 11:12:03 am »
I think I mentioned that  :)
The original one is there C11 and R7.
I am talking about a snubber across the MOSFET.
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Offline Zog

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #38 on: May 20, 2018, 11:13:38 am »
Of course.
Please read back a few pages.
It has been mentioned  :)
Indeed it has even been drawn !  :)

Edit: this is the droid you are looking for master skywalker
https://www.eevblog.com/forum/projects/design-of-smps-not-sure-what-these-spikes-are-being-caused-by/msg1550420/#msg1550420

P.S. do you have any clues as to why a center tap would reduce the amps out ?   ;D
« Last Edit: May 20, 2018, 11:19:11 am by Zog »
 

Offline b_force

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #39 on: May 20, 2018, 11:50:56 am »
Of course.
Please read back a few pages.
It has been mentioned  :)
Indeed it has even been drawn !  :)

Edit: this is the droid you are looking for master skywalker
https://www.eevblog.com/forum/projects/design-of-smps-not-sure-what-these-spikes-are-being-caused-by/msg1550420/#msg1550420

P.S. do you have any clues as to why a center tap would reduce the amps out ?   ;D
Ok, my apologies.
It's not showing in the schematic in your last post, so that's a little confusing ;)

With the center tap probably something has to do with halving the inductance maybe
With a center tap I would suggest using a higher value.
« Last Edit: May 20, 2018, 12:44:39 pm by b_force »
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Offline Zog

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #40 on: May 20, 2018, 11:55:59 am »
No probs "brah"  :)
Thanks for the clue !
Cheers,
Phill from W.A.
 

Offline b_force

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #41 on: May 20, 2018, 12:48:48 pm »
No probs "brah"  :)
Thanks for the clue !
Cheers,
Phill from W.A.
You can simulate these kind of things pretty easy btw.
"If you can't explain it simply (or at all), you don't understand it well enough." A. Einstein

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Offline Zog

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #42 on: May 20, 2018, 01:35:32 pm »
Yes.. I have tried in TI workbench.
But no result.
Spice is probably better but how many trees must I chop down to see the forest ?
 

Offline T3sl4co1l

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #43 on: May 20, 2018, 03:01:13 pm »
Building a representative model in a simulator does take some knowledge of the simulator itself, and trust in the models (or preferably, verification -- and knowing how to do that).

The ringing you are seeing is common mode, there's no reason for that signal to be on that pin as such (it has a capacitor to ground across it!).  That's just ringing you will probe literally anywhere in the circuit -- because it's actually voltage drop across the probe's ground lead!

Reducing drain rise time will address that.  Hence the RCD rate subber I drew. :)

Output current: probably lower because primary inductance is lower?  A 50% tap gives Lp ~= 25% of total inductance.  Maximum peak current remains the same, so you get less energy per cycle = less average power.  Ideally what you'd have done: wind the same (or more) number of turns on top. :)

Tim
« Last Edit: May 20, 2018, 03:04:26 pm by T3sl4co1l »
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Offline Zog

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #44 on: May 20, 2018, 06:38:38 pm »
Yes of course ... 1/4 the inductance not 1/2 I see now.
Will get winding.

I have a very nice LCR meter with kelvin clips .. so should be able to get a good job done.

Which ringing are you talking about ?
The one on test point 2 or 3 ?
 

Offline b_force

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #45 on: May 20, 2018, 06:42:22 pm »
Output current: probably lower because primary inductance is lower?  A 50% tap gives Lp ~= 25% of total inductance.  Maximum peak current remains the same, so you get less energy per cycle = less average power.  Ideally what you'd have done: wind the same (or more) number of turns on top. :)

Tim
That's the part you can simulate.
Just cut your model down, and change the value of the inductor and see what it does.

The ringing is a different story, although there are guidelines to figure where to look.
Just google on it, so many great articles and papers about it.
"If you can't explain it simply (or at all), you don't understand it well enough." A. Einstein

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Offline Zog

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #46 on: May 20, 2018, 06:54:18 pm »
You are right. Many great articles on it.
Trouble is you can't ask an article a question.

Hence why this forum is what it is.
A great way for people to help each other out about the things they don't understand just by reading them.

No need for teachers if we could all just read it in a book right ?

The "just google it" seems to be a catchall these days. It's good but not always the best way to get the exact knowledge you seek.
I am sure you agree. I have seen some of your posts  ;)
« Last Edit: May 20, 2018, 06:56:34 pm by Zog »
 

Offline b_force

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #47 on: May 20, 2018, 07:00:52 pm »
You are right. Many great articles on it.
Trouble is you can't ask an article a question.

Hence why this forum is what it is.
A great way for people to help each other out about the things they don't understand just by reading them.

No need for teachers if we could all just read it in a book right ?

The "just google it" seems to be a catchall these days. It's good but not always the best way to get the exact knowledge you seek.
I am sure you agree. I have seen some of your posts  ;)
Yes I agree, and I don't often say it, but in this case I do believe there are some papers out there that will explain and summarize much better than I can.  8)
"If you can't explain it simply (or at all), you don't understand it well enough." A. Einstein

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Offline Zog

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #48 on: May 20, 2018, 07:02:42 pm »
Indeed ,and if you had followed the thread from the start, you would see that someone has already provided what I think is one of the best ones out there in this very thread !
« Last Edit: May 20, 2018, 07:10:43 pm by Zog »
 

Offline b_force

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #49 on: May 20, 2018, 07:22:57 pm »
Indeed ,and if you had followed the thread from the start, you would see that someone has already provided what I think is one of the best ones out there in this very thread !
I don't really follow what you're referring to.
I did read the thread, but haven't seen a solution yet?

Anyway, doesn't matter.
The point is, with switching supplies a lot comes down to the PCB design and which parts you choose as well.
I will dive into my pile of papers later do show a better understanding of it  ;) :)
"If you can't explain it simply (or at all), you don't understand it well enough." A. Einstein

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Offline Zog

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #50 on: May 21, 2018, 10:45:13 am »
Ok .. I now have 125 mA's out as per your instructions Tim,
Well done on picking that up for me.

The gate still shows ringing of course but the FET run's very cool now which is a big plus.
Zero missing pulses.

The guys design runs at slightly below the recommended chip frequency.
I might try to up that a bit. His reasoning was the gate charge even though pretty low would lower the efficiency.
What's your opinion ? I would rather up it and use smaller inductors.

I am now experimenting with different winding ratios and will report back.
Once I have got that down I will start implementing the rest of your suggestions.

After that I will continue with the suggestions on layout posted before.
The dirty ground net naming trick is a good one I have never seen anywhere else.

You were also right about that other signal. It is all over the board anywhere you poke the probe. Layout of course.

Cheers mate.
 

Offline T3sl4co1l

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #51 on: May 21, 2018, 02:00:30 pm »
Gate charge is a tiny part of overall switching loss, far more significant is the stray inductance causing RF to blast out of everywhere!

As the leakage inductance is part of that switching loss (unless clamped and recycled -- an advanced topic), you can't reduce losses terrifically far in this type of design.  A good transformer is required.  Still, it should be able to run at 200kHz easily, given improved layout and an okay transformer.

Adding gate resistor(s) is necessary with the layout as-is, as this reduces the switching speed.  You must slow it to below the rate of that ringing, so as not to excite it.  Then your waveforms will look alright.

Tim
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Offline Zog

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #52 on: May 21, 2018, 08:31:33 pm »
Thanks Tim,
Yes a gate resistor was mentioned by someone else too.

Is that in addition to the snubber on the gate or can that be the "gate" resistor. I am assuming it can be/is.

BTW A Zero poster called Carlotta sent me a PM pushing their "prototyping" service.
 https://www.smart-prototyping.com/. You can also contact me at carlota@smart-prototyping.com
Anyone else heard of this crowd ?.
I am pretty happy with my current manufacturer, so doubt I will change.
« Last Edit: May 21, 2018, 08:33:09 pm by Zog »
 

Offline T3sl4co1l

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #53 on: May 21, 2018, 08:55:26 pm »
Thanks Tim,
Yes a gate resistor was mentioned by someone else too.

Is that in addition to the snubber on the gate or can that be the "gate" resistor. I am assuming it can be/is.

Some kind of gate resistance, yes.  If it's two resistors and a diode, or just a resistor, whatever, that's just different ways of getting there, more options.

Quote
BTW A Zero poster called Carlotta sent me a PM pushing their "prototyping" service.
 <snip free advertising> You can also contact me at carlota@SPAM
Anyone else heard of this crowd ?.
I am pretty happy with my current manufacturer, so doubt I will change.

Same.  Mods, if you would please -- discipline said account for PM spam?

Tim
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Offline Zog

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #54 on: May 21, 2018, 09:11:49 pm »
Roger roger,
Thanks Tim.

I will "go dark" on this topic for a few weeks now.
Need to get a new board layout done for testing.
Source parts etc.

Will be back once this is done.
Cheers,
Phill
 

Offline Zog

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #55 on: August 17, 2019, 12:50:58 am »
Hi All,
I have given up trying to make this myself and need a pro to do it for me, preferably in Eagle. (paid job)
Need 100 Watts.
Anyone interested ?
 

Offline treez

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #56 on: August 17, 2019, 04:24:33 pm »
Your vout is 185VDC
Your Pout is 100w
Your vin is =12v?

Have you thought of the dual cascaded boost?
Ill  send you some stuff on it if you want.

(I am working through the three pages to see where you got stuck....i saw you were wondering about winding a tapped inductor at one point, and at one point you were speaking of a noise issue.
, you gave a website of a cct you "copied"?...
https://jan.rychter.com/high-voltage-power-supply-for-nixie-tube-projects
)
« Last Edit: August 17, 2019, 11:08:32 pm by treez »
 

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #57 on: August 17, 2019, 05:34:58 pm »
Hi All,
I have given up trying to make this myself and need a pro to do it for me, preferably in Eagle. (paid job)
Need 100 Watts.
Anyone interested ?

Is this still for Nixie tubes, which require approximately 10mA each? So 100W would be good for around 50 of them?!?

Input voltage? Size constraints? Budget? I likely have something in my pile of past projects that can be easily modified for the job, and I use EAGLE 7.7 (ie - the last version before getting Borg'ed by Autodesk), but I am a bit busy for the next couple of weeks.


 

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #58 on: August 17, 2019, 10:55:54 pm »
If you give the input voltage, then ill send you a design, and you can see if you want to go on and do it yourself, or contact myself.

PCB layout doc attached...did you follow these rules?

I must admit im an eagle 7.4.0 user.

Also,  there is the cascaded boost, which i could modify for you if you wish...its as attached
« Last Edit: August 17, 2019, 11:12:13 pm by treez »
 

Offline Zog

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #59 on: August 17, 2019, 11:35:00 pm »
@treez
Quote
If you give the input voltage, then ill send you a design, and you can see if you want to go on and do it yourself, or contact myself.
I don't have the skills to try to do it myself.

@treez
Code: [Select]
Also,  there is the cascaded boost, which i could modify for you if you wish...its as attachedOnly text in that file ?

@MagicSmoker
Code: [Select]
Input voltage? Size constraints? Budget? I likely have something in my pile of past projects that can be easily modified for the job, and I use EAGLE 7.7 (ie - the last version before getting Borg'ed by Autodesk), but I am a bit busy for the next couple of weeks
Input voltage can be from 5VDC to 24VDC. Size ? about the size of a packet of cigarettes. Output Voltage 220VDC because I want to drive a doubler circuit to get 440VDC for Dekatrons.
 

Offline MagicSmoker

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #60 on: August 18, 2019, 11:24:52 am »
...
Input voltage can be from 5VDC to 24VDC. Size ? about the size of a packet of cigarettes. Output Voltage 220VDC because I want to drive a doubler circuit to get 440VDC for Dekatrons.

A nearly 5:1 input voltage range is absurdly impractical. The only commercial supplies that accommodate anywhere close to that are universal input flybacks that can run on 85VAC to 265VAC, and even that is "only" a 3:1 range. Cramming 100W into the volume of a cigarette box is also going to be challenging, especially with the input voltage restriction.

Do you need the 220V and 440V at the same time, or is it an either/or thing?


EDIT - fat-fingered posting before finishing.
 

Offline treez

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #61 on: August 18, 2019, 12:39:24 pm »
yes, 100W from a 5V input means >20A of input current. Size may need to be bigger, but if it can be a wide pack of cigarettes, then we may be able to get near it.

Quote
Only text in that file ?
(The .txt file you can change to .asc, then  open in the free LTspice simulator)
« Last Edit: August 18, 2019, 12:43:30 pm by treez »
 

Offline Zog

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #62 on: August 18, 2019, 10:32:04 pm »
Quote
A nearly 5:1 input voltage range is absurdly impractical. The only commercial supplies that accommodate anywhere close to that are universal input flybacks that can run on 85VAC to 265VAC, and even that is "only" a 3:1 range. Cramming 100W into the volume of a cigarette box is also going to be challenging, especially with the input voltage restriction.

Sorry I didn't make myself clear.
That voltage range is what I can deal with in terms of getting another small  DC power supply to drive it.
In other words I would be getting a separate commercial one to convert 110/240VAC to the DC provided for this design. I was thinking of just buying a meenwell or other reputable brand for the DC input.
Quote
Do you need the 220V and 440V at the same time, or is it an either/or thing?

I need both at the same time.


 

Offline Zog

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #63 on: August 18, 2019, 10:38:09 pm »
I just found this one on ebay. I have not done a search for a while.
eBay auction: #https://www.ebay.com.au/itm/High-Voltage-DC-DC-150V-420V-Converter-NIXIE-Tube-HV-Power-Supply-1-25-12V-adj/333261626043?hash=item4d97f0dabb:g:UKMAAOSwPbldTjVL
Could I just put two or more of these in parallel to get the mA's I need ? Is that possible ? Common mode problems ?
Might be a quick and dirty way to do it ?
« Last Edit: August 18, 2019, 11:46:52 pm by Zog »
 

Offline Zog

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #64 on: August 18, 2019, 11:44:30 pm »
yes, 100W from a 5V input means >20A of input current. Size may need to be bigger, but if it can be a wide pack of cigarettes, then we may be able to get near it.

I don't have a preference for input voltage.  Looking at a mean well supply 12V or 24V DC to power it. They are quite small and are high wattage.

Quote
Only text in that file ?
(The .txt file you can change to .asc, then  open in the free LTspice simulator)

LT Spice is wayyy beyond me !
 

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #65 on: August 19, 2019, 01:26:12 am »
The spikes in the middle of the ramp may be real.  There are some other, taller, spikes that are very narrow.  These may not be real.
First check is to connect the probe ground to your normal ground point, and then clip the probe tip to the same point.  if you see a bunch of spikes, these are coming through the GROUND of the probe, NOT through the signal pin of the probe.  That causes current through the ground shield of the probe.  You need to improve the ground between the ground point on the scope and the ground point of the equipment under test.

Jon
 

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #66 on: August 22, 2019, 02:14:42 am »
Quote
The spikes in the middle of the ramp may be real.  There are some other, taller, spikes that are very narrow.  These may not be real.
First check is to connect the probe ground to your normal ground point, and then clip the probe tip to the same point.  if you see a bunch of spikes, these are coming through the GROUND of the probe, NOT through the signal pin of the probe.  That causes current through the ground shield of the probe.  You need to improve the ground between the ground point on the scope and the ground point of the equipment under test.

Thanks for that. It was pointed out before but I appreciate your input.
 

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #67 on: August 22, 2019, 02:19:34 am »
This image is a little unclear.
Anyone have any idea what the main driver chip is ?



« Last Edit: August 22, 2019, 02:24:41 am by Zog »
 

Offline T3sl4co1l

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #68 on: August 22, 2019, 03:23:15 am »
TL494 or similar.

Tim
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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #69 on: August 22, 2019, 04:01:51 am »
Tim,
This is the circuit I came up with after you supplied me those hand drawn sheets.
Does this look right to you in general connections terms  ?

 

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #70 on: August 22, 2019, 04:36:16 am »
C8 charges when Q2 turns on, which will probably defeat the peak current mode operation of the controller.

They also don't document it very well, but TPS40210 goes into hiccup mode (/SS pulls low, stays off until crosses rising threshold) rather than current limiting.  It's rather dumb.

The combination will probably frustrate operation of this circuit enough that it never starts up, or doesn't maintain the full output you were expecting, or isn't able to recover from a momentary overload condition.

You can use multiple secondaries as their own flyback outputs, and connect the DC outputs in series.  Then you don't need C8 charging on the "down stroke", energy gets delivered to the output only in the flyback period (Q2 off).  Probably use N = 2-3 of say MSS12xx dual-winding inductors, with the primaries in parallel, and the secondaries wired accordingly.  (Choose inductance to be N times higher per inductor, because for uncoupled inductors, the value reduces in parallel.)

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #71 on: August 22, 2019, 04:42:20 am »
Thanks Tim,
That explains why it never started up.
Will look at implementing your new suggestions.

The circuit is wired correctly though right ?

Quote
You can use multiple secondaries as their own flyback outputs, and connect the DC outputs in series.  Then you don't need C8 charging on the "down stroke", energy gets delivered to the output only in the flyback period (Q2 off).  Probably use N = 2-3 of say MSS12xx dual-winding inductors, with the primaries in parallel, and the secondaries wired accordingly.  (Choose inductance to be N times higher per inductor, because for uncoupled inductors, the value reduces in parallel.)

Could you perhaps provide a hand drawn circuit explaining to us non engineers just what you mean by that ?

Quote
C8 charges when Q2 turns on, which will probably defeat the peak current mode operation of the controller.

It did not do that on the original circuit ? Little confused now ?    :-// (original is the original post)
« Last Edit: August 22, 2019, 05:07:37 am by Zog »
 

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #72 on: August 22, 2019, 08:10:28 am »
Other than that, yeah I think so.

There was an appnote I think from TI's "flybuck" documentation that showed the connection, I can't seem to find it offhand.  Try giving that a look.

Yes, the original circuit would have the same problem.

Tim
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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #73 on: August 23, 2019, 09:38:58 am »
I thought these files might help other beginners like me at how to layout SMPS. treez layout instructions are very good. https://www.eevblog.com/forum/projects/design-of-smps-not-sure-what-these-spikes-are-being-caused-by/msg2622906/#msg2622906

The TPS40210 Datasheet http://www.ti.com/lit/ds/slus772f/slus772f.pdf is good but kind of difficult to follow given that the example circuit does not match the layout. The example layout is just the bottom and the top, so I got creative in photoshop and merged them together and added component references so it's a little easier to follow.
Pretty sure it's a hexfet package used for Q1.





Top and Bottom layers merged.



Top Layer


Bottom Layer


I do have a question though.
What are the R1,R2 and the jumper for ?








« Last Edit: August 23, 2019, 10:04:21 am by Zog »
 

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #74 on: August 23, 2019, 06:51:05 pm »
Looks to be routed to EN. Don't know why it's not on the schematic.

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #75 on: August 23, 2019, 09:30:57 pm »
Quote
I don't have a preference for input voltage.  Looking at a mean well supply…

OK so I take   it your power source will be an offtheshelf power supply from eg meanwell.
You could get the LRS-150-48….
https://www.meanwell.com/webapp/product/search.aspx?prod=LRS-150
This has a 48V output.
Then you  just need to boost up from 48V to your 185V, 100W output.
 
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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #76 on: August 24, 2019, 03:43:12 am »
Thanks treez,
The biggest problem at the moment is layout.
You mentioned you have an eaglecad 7x version.
Is it possible to export my version 9x back to eagle 7x for you to have a look at ?
 

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #77 on: August 24, 2019, 08:26:45 am »
Hi,
Yes i can try and open it in my eagle here. Ill have a look, yes.
 
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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #78 on: August 24, 2019, 10:18:27 pm »
Hi Zog,
As was discussed, your  vin = 12v, vout = 220v and pout = 100w. Your chosen  topology is the tapped boost.

One problem  for the tapped boost with such high “primary” current  (around 14A peak in your case) is that unless you can ensure very tight coupling between the two sections of the tapped inductor, then you are going to get high voltage spikes on the drain of the fet whenever it turns off. I think you may  need  (depending on your actual coupling) to put a clamp across the primary side of the tapped inductor as in the attached. The bare  basic schematic is attached…also the LTspice simulation. This is a free  download  simulator and you will find it very easy to use.
Just  open the simulation (.asc file)  and hit the running man icon….then click away at your leisure to see the circuit voltages and currents…ALT, Left click to see the power…….its a lot easier than that TI webbench one.
 Its always best to run some kind of representative simulation of a SMPS first before going to the bench. If an SMPS works on the simulator, then it doesn’t mean it will work on the bench, but generally, if you cant get some kind of representative simulation working first, then its  often  a waste of time going to the bench. All the best SMPS engineers ive worked with  at places like Alcatel, Tridonic, etc etc are avid users of simulators…….if only just to check over what you are about to do on the bench.
I think  a tapped boost inductor at the current levels here, would  preferably need to be interleave wound to increase coupling….otherwise I suppose you can just have a chunky clamp resistor and just eat up the leakage energy like that.
Your vin is only 12v, and your peak fet current is going to be in the region of 14A or so…….so you will need a fet with low rds(on)….but also, if you are getting high voltage drain spikes  due to the leakage inductance, then you will need the fet to be rated to that high voltage….the problem is that low rds(on) fets are often not available with high voltage ratings.

Anyway, if you dont use a fet with low enough rds(on), then you are just not going to get enough power throughput, as the volt drop in a high rds(on) would mean your effective input voltage is even lower than 12v.......this would get worse as the fet warms up and its rds(on) increases.
One of your schems shown here shows a fet with 3 ohms rds(on), and thats the min value.....you wont be able to get much current through that from a 12v input.

This is one  of the reasons doing a sim first is good.,...it flags up points like that which are so easy to forget.

This is why I believe that the Dual Boost converter is better for you, and I have provided  details in a following post. In the Dual boost converter…the   fet that sees the higher current only sees a low voltage, and so you can easily find suitable fets. Also, the Dual Boost doesn’t have coupled coils, so leakage inductance does not have to be dealt with.
Leakage inductance isn’t too bad when not much current flows in it…because the energy of the leakage inductance is i^2.R. But with your high-ish peak current, you could end up with high leakage energy to dissipate….depending on how well coupled are your coils.
Even with a tapped boost, the high step up ratio is likely to mean that you will need slope compensation. If you  pick a constant off time controller then you won’t need to use slope compensation.
« Last Edit: August 24, 2019, 10:43:47 pm by treez »
 
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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #79 on: August 24, 2019, 10:28:07 pm »
I think for vin=12v, vout = 220v, pout = 100w, you are better  off with the dual Boost converter as  in the attached….

....either using constant frequency operation, or constant off time (COT) …….const freq needs slope compensation, COT does not.
The dual boost is very good because the fet that sees the higher current sees a lower voltage, so you can easily find low rds(on) ones. This is important for you since your vin is so low……any volt drop in the rds(on) will subtract from the input voltage and make it even  lower. The Dual boost only uses one controller as shown. LTspice simulation also attached. It just uses simple inductors..no coupling required.
 
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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #80 on: August 24, 2019, 10:30:15 pm »
LTspice quick start guide attached if you need it....you easily have the knowledge to be able to run a LTspice sim and view the circuit voltages and currents.
If you   want to run it, just open the .asc file and hit the running man icon....when youve finished, delete the large .wav file or  else your hard disk will eventually  fill up if you keep running different sims.
« Last Edit: August 24, 2019, 10:32:15 pm by treez »
 
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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #81 on: August 25, 2019, 12:04:48 am »
HOLY HAND GRENADE BATMAN ! ;D ;D ;D

You my friend, are a true legend and not just in your own underpants !

You have been busy haven't you.

Time to have another crack at LTSpice.

I don't quite know how to thank you for this. A forum thanks does not seem adequate.

But THANKS ! :-+ :-+

I will of course keep you posted on how I go with this.

P.S. early versions of eagle will not open later versions as far as I know.

edit:
Mate I am loving this LTSpice !
Your quick start guide and the circuits you have supplied have made it so easy now to adjust component values.
I have been thinking of making the rsense divider network adjustable using a trim pot for example.
Now I just have to change the values to see what range I can adjust it to and look at the wave forms.
TI Workbench is rubbish compared to this.
Thank you so much for suggesting the UCC28C43 as a replacement too. It's datasheet layout guide is so much easier to understand that the chip I was using for the other design.

I have a few more questions if I may impose on you again.
Why would I use the constant frequency over the over the constant off time circuits. Does one have any advantages over the other ?
I don't see much difference in the output ?

Constant time off (no slope compensation)


Constant frequency (slope compensation)




The tapped boost is confusing me too. How would I get the pulse into the mosfet ? (custom pulse circuit ?)

« Last Edit: August 25, 2019, 06:08:14 am by Zog »
 

Offline treez

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #82 on: August 25, 2019, 09:59:29 am »
Quote
Why would I use the constant frequency over the over the constant off time circuits. Does one have any advantages over the other ? I don't see much difference in the output ?

Yes in this case it doesn’t matter too much…COT is more helpful when there is a wide range of Vin (or wide range of vout)…COT means that  in cases of wide vin range, the  increase of duty cycle wont be as unmanageable as with a constant frequency converter….typically, as duty cycle increases, the off-time gets less with a const freq converter, and sometimes there is a limit to how low the off time can get…so if you have a COT converter……well, your off time is fixed to an acceptable level in the first place, so its never going to get ridiculously small…….however, it does mean that your switching frequency changes as the vin changes……with COT you have to examine all conditions of load and line to tell that your switching frequency never gets too ridiculously high.
Another point is that COT converters don’t ever need slope compensation…….which means you don’t have to  bother with that.

Another point is that there's not many COT pwm controllers on the market off the shelf....the LT1248 that i show  in the sim is a const freq converter that i hacked in the sim to work in COT.
The HV9910B is another COT chip
Onsemi do one also.
But there arent many others.

The Tapped Boost is attached here in LTspice sim.......it takes ages to run unfortunately.....and if you put in the leakage inductance by going "K L1 L1 0.99", it then takes even longer.
There arent FETs in LTspice with high enough voltage and low enough rdson........so i have to make a behavioural source and just drive loads of high rdson fets in parallel...(like i did in the previous  abbreviated tapped boost sim)
With the tapped boost attached here, if you add in the leakage inductance , the fet then  gets overvoltaged.....by the leakage spikes....so then you have to change to a 600v fet.....but then its rdson is  too high....so you then have to  go adding more in parallel ...and then of course theres too much  gate capacitance for the pwm chip to drive...so you then have to add a behavioural source to  mimic the pwm controller output.
« Last Edit: August 25, 2019, 10:15:14 am by treez »
 
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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #83 on: August 25, 2019, 10:23:52 am »
Note the downside to constant-time and hysteretic converters: the ripple is all over the place, especially at the operating extremes.  At high frequency, switching loss is more significant; at low frequency, reactive losses are more significant (inductor core/winding loss, filter cap ESR), and input and output voltage ripple/noise.

Controllers with reasonably well bounded frequency are easier to design filters for.  They're also easier to observe on the oscilloscope, which is probably helpful in development.

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #84 on: August 25, 2019, 10:49:37 am »
Oops sorry, i used the wrong diode in the tapped boost simulation, please find the corrected version here.
 

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #85 on: August 25, 2019, 11:06:26 am »
top of page 4 of this
http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.913.7541&rep=rep1&type=pdf

shows how you can measure your tapped inductor coupling coefficient, k.

This is important as it affects the duty cycle needed to get from vin to vout......too much leakage and your D max may not be big enough for you to get vout from vin

(woops, just realised i accidentlaly wrote "overlap" instead of "overload" in the above simulations annotation, i also accidentally called the "tapped boost" a "tapped buck" simulation...sorry about that)
« Last Edit: August 25, 2019, 01:59:27 pm by treez »
 

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #86 on: August 25, 2019, 02:00:41 pm »
I am confused again.

After running your new update in LTSpice I see significant changes and was wondering what caused the changes.

The original sim had a nice slow startup from zero volts and was stable at 9ms.


Original V4


The corrected version shows this. I did turn off the Skip initial operating point solution to show it a little more clearly but is only nearly stable at 30ms.



Revised V4


I made up a little voltage divider with these values and replaced V4 in the original with it and it worked well.


What benefit is this ? I took it out and it made no obvious difference  to the output ?









« Last Edit: August 25, 2019, 02:02:43 pm by Zog »
 

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #87 on: August 25, 2019, 02:15:02 pm »
So you are comparing the tapped boost with one of the dual boosts.....i confess i havent bothered changing the feedback compensation components for the tapped boost...and the dynamics of the tapped boost are likely to be more  complex than the dual_boost.....so i reckon the tapped boost could be speeded up by changing the feedback compensation components......

The LTC6101 based circuit is purely for startup and  overload.........it stops the "staircasing" of the inductor cuirrent at startup which is prevalent in many smps's when they are starting up and the vout is well below what it shoudl be.,............its the vout which "discharges" the inductor so if its not  high enough you get too high currents in the power stage...therefore i put in the ltc6101 sensor and the extra error amplifier to limit the current........but it will just lie dormant when the converter has got started.

It sounds like you have hacked it to be in current limit mode all the time by reducing the 2.8volts to 0.5..........thats isnt what the current limiter is meant for.

So also you coudl try clicking the ".ic v(out) = 220v" and make that a comment instead  of a spice directive...that may speed it up.......but otherwise i think the complex dynamics of the tapped boost mean the feedback compensation components need changing to make it startup quicker and oscillate less during startup.

The little filter inductor L3, is purely to keep the current ripple out of the sense resistor of the ltc6101 current monitor...and of course, this only operates at startup (or overload)...so yes, ususally this doesnt do much...(but woudl be good for emc in a real converter)
I dare say the ltc6101 probably works well enough if L3 is omitted.
(Apologies for my fat finger typing in places.)
« Last Edit: August 25, 2019, 02:26:40 pm by treez »
 
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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #88 on: August 25, 2019, 02:40:31 pm »
Thanks again treez,
I changed the V4 to a voltage divider in the Dual Boost original. Is that ok ?
 

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #89 on: August 25, 2019, 03:03:54 pm »
...yes as long as the voltage is the same.....it only goes into an opamp input, and as you yknow, these are very high impednace, so no problems with the divider here.....it just sets the limit that the input current is set to, so that you dont get too much current at startup...after that the error amp concerned just goes dormant.

By the way, if you like, there is my free switch mode power supply course which explains a lot about SMPS's....
https://drive.google.com/open?id=0B7aRNbu3Fes4TU92Mkw3YlA3ams

{...always interested to here if all course folders from A to Z (sorry, "Y")  got sucessfully downloaded, so please  say  if the download didnt work}

Here is also my guide to doing an electronics degree
https://massey276.wixsite.com/electronicsdegree
« Last Edit: August 25, 2019, 04:02:51 pm by treez »
 

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #90 on: August 26, 2019, 06:52:17 am »
treez,
Something wrong with your latest Dual Boost ?
Only showing 210mW output ?



 

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #91 on: August 28, 2019, 09:44:30 am »
I am an idiot.
No load in sim.
Just got back to working on it. shows 100W as advertised.
 

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #92 on: August 29, 2019, 10:11:08 pm »
Quote
By the way, if you like, there is my free switch mode power supply course which explains a lot about SMPS's....
https://drive.google.com/open?id=0B7aRNbu3Fes4TU92Mkw3YlA3ams

WOW. So much information and a great course treez.
I was wondering on how to do so many things and having a skim through it I found many answers to my questions. Well done mate.

So many links to great resources. Spreadsheets and on and on and on. If you made it into a wiki I think you would be the number one resource for beginners like me.
I won't be asking so many questions now (I hope) that I have this little gem in my pocket.

I was wondering how to make the supply into a 25W one for instance and putting two or more in parallel to get more power if I need it and I now have the info I need.

Not found out how to lower the output to 25W yet though. But will keep digging, I am sure it's in there somewhere. Probably just mucking around in spice and selecting different components.

Layout is still my biggest hassle. I am still working on that, but there are lots of resources to calculate currents in tracks etc. So I might eventually get through that barrier.

Quote
Here is also my guide to doing an electronics degree
https://massey276.wixsite.com/electronicsdegree

At 59 it's a little late for me. Particularly as maths is not my strongest point.

Cheers treez.
« Last Edit: August 29, 2019, 10:13:17 pm by Zog »
 

Offline Zog

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #93 on: August 30, 2019, 05:22:24 am »
Did not take long.
Another question.
In spice when looking at the current through L2 should I be selecting an appropriate inductor based on Average current or RMS.
I am presuming RMS correct ?

And that current should be less than the saturation current I am guessing.

edit: stupid question. should be RMS given the wave shape.
edit2: .. err.. shouldn't it ? :scared:

More editing:
Looking at this one for L2 in the tapped buck
https://www.digikey.com.au/product-detail/en/pulse-electronics-power/PE-54036SNL/553-1419-ND/1037030
« Last Edit: August 30, 2019, 05:55:48 am by Zog »
 

Offline MagicSmoker

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #94 on: August 30, 2019, 09:42:21 am »
...
In spice when looking at the current through L2 should I be selecting an appropriate inductor based on Average current or RMS.
...

Neither: it is the peak current that is most important in selecting the inductor, as that determines the energy handling requirement. RMS current is relevant only in selecting the wire diameter.
 
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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #95 on: August 31, 2019, 07:46:02 am »
Thanks for clearing that up magic.
I removed the previous post because it was a silly mistake on my part.
I figured that little problem out and didn't want to clutter up the forum.
 

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #96 on: August 31, 2019, 10:51:16 pm »
Having trouble stepping the output load in LTspice

Not sure what I am doing wrong but I want to be able to step the load to see the transient analysis.
I have looked all over google and can't find a definitive answer.

I am not sure how or where to set the flagloads option to flag the external current source to be a load.


« Last Edit: August 31, 2019, 10:52:58 pm by Zog »
 

Offline T3sl4co1l

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #97 on: September 01, 2019, 03:49:16 am »
Use the PULSE type.  Alternately, use some resistors, a switch and a VPULSE.

Tim
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Electronic design, from concept to prototype.
Bringing a project to life?  Send me a message!
 
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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #98 on: September 01, 2019, 10:57:32 am »
Having trouble stepping the output load in LTspice

There's a couple ways to do this, but I like to use a the voltage controlled switch model ("SW") driven by a pulse source.

You need to include a .model statement in your circuit which specifies the relevant parameters for the switch like so:

.model SW SW(Ron=1m Roff=10Meg Vt=4 Vh=-1)

And then drive it with a voltage pulse source that delivers 10V when on, has the rise and fall times you desire, etc.
 
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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #99 on: September 01, 2019, 12:32:11 pm »
Thank you very much MagicSmoker and Tim,

That was a great way to do what I wanted and by providing the .model example I had it completed in 1/2 Hour.
I don't want to "bless" you all with my appalling Frankenstein of a hack just yet so will show you the bit that did the trick.



Look at that lovely disruption.  :clap:



P.S. I have to thank treez for getting me into LTSpice too. If he had not provided me with a starting point I would never have got anywhere. Everyone needs a "hello world" to get going !




« Last Edit: September 01, 2019, 12:38:57 pm by Zog »
 

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #100 on: September 01, 2019, 01:36:48 pm »
Looks like it's sitting pretty deep in cutoff, when unloaded.  Which makes it take a long time to throttle up.  Try putting some preload on it, like a resistor or CCS of 10% of nominal load.

Tim
Seven Transistor Labs, LLC
Electronic design, from concept to prototype.
Bringing a project to life?  Send me a message!
 

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #101 on: September 01, 2019, 01:46:35 pm »
Thanks Tim,
Just mucking around with spice at the moment. Trying different ideas and different inputs to see how to drive spice, but I will do just that and post my results as usual.  :-+

edit:
I did just want to see just how hard I could hammer it too.
Nixie tubes are not that fussy about voltage spikes in the output. (to a point of course)
« Last Edit: September 01, 2019, 01:50:20 pm by Zog »
 

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #102 on: September 17, 2019, 01:59:02 pm »
Quick question guys.
I am getting in pretty deep with LTSpice now and was wondering what K coupling factor I should put in if I use two seperate inductors connected with a very short wide trace at the switch node ?
I kinda figure it won't make a lot of difference if they are really close right ?

Another one is putting in the values for the inductors ? At the moment they are just set at their nominated series resistances. Does putting peak current in make much of a difference or parallel ? I am guessing not much unless you are getting really nitty gritty and working with very complex inductor arrangements and not just my 2 effectively in series ?
 

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #103 on: September 17, 2019, 02:20:17 pm »
Quick question guys.
I am getting in pretty deep with LTSpice now and was wondering what K coupling factor I should put in if I use two seperate inductors connected with a very short wide trace at the switch node ?

Is this a dual boost or tapped boost? I kinda forgot which direction you ended up going here. At any rate, if a dual (probably best to say cascaded) boost then there is no coupling between the boost chokes; if a tapped boost then "it depends" noting that the leakage factor is approximately 1-(K2). So, for example, if K=0.9975 then leakage factor will be 0.005 (or 0.5%). This is typical for a single layer tapped-winding on a toroid.

Another one is putting in the values for the inductors ? At the moment they are just set at their nominated series resistances. Does putting peak current in make much of a difference or parallel ? I am guessing not much unless you are getting really nitty gritty and working with very complex inductor arrangements and not just my 2 effectively in series ?

??? Not sure what you are asking about here...

EDIT - I guess you are talking about the "secondary" parameters for the inductances? I advise specifying a realistic value for the series resistance but leave all the other stuff alone for now.
 
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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #104 on: September 18, 2019, 04:05:55 am »
Thanks for clearing that up Magic,
Tapped is what I am going for but only for the reason that they mention that - in general - flybacks are only good for 50W and forward converters are good for 150W. I read it somewhere can't remember where.
I have been getting good results from treez Dual Boost 12V to 220V at 100W_TAPPEDBUCK_CONST FREQ_1 though the part count is kinda high.

So me .. being me and and wanting to push the boundaries of just what I could do found this chip LT3757A https://www.analog.com/media/en/technical-documentation/data-sheets/3757afe.pdf.
What a little beast. One resistor for setting the clock. Wow.
I have made about 5 or so different versions of flyback and tapped boost but can come no where near the circuit treez gave to the group.

The problem I am having with the dang thing is that it will NOT keep the fet on long enough to get the inductor "saturated".
I have tried all sorts of things.

Frequency has no effect no matter how fast or slow you run the thing.
Different inductor ratios.
And on and on. Been at it for days and I don't think this thing will do it.

Pity, as is has a nice low input voltage of 2.9V up to 40V.
I have attached my latest version. Have not bothered with snubbers or gate control. Have tried all that and has no effect because the Fet just will not stay on long enough.

Is there a way I could MAKE is stay on longer. Is that even the problem ?

Happy snaps of my abomination in action.


Nice if you like rainbows. The Red trace is the Gate.


edit:
This part of the datasheet is kinda, maybe a clue ?
VC Current Mode Gain (∆VVC /∆VSENSE) 5.5 V/V
VC Source Current VFBX = 0V, VC = 1.5V –15 µA
VC Sink Current VFBX = 1.7V
VFBX = –0.85V

Or maybe a cap on the gate to lengthen the pulse somehow ? Zero clue on how I would do that though. Duty Cycle does not seem to be an option.

Edit: Again.
I think I have found my problem. Apart from the fact I can't read a data sheet properly.
Looks like it's already at almost 100% DC.

Quote
For a boost converter operating in CCM, the duty cycle
of the main switch can be calculated based on the output
voltage (VOUT) and the input voltage (VIN). The maximum
duty cycle (DMAX) occurs when the converter has the
minimum input voltage:
DMAX =
VOUT − VIN(MIN)
VOUT

More editing.
I changed the inductor ratio to 1:3.
But would you be happy with this waveform ? I mean what on earth is causing this constant ringing in the inductors ?









« Last Edit: September 18, 2019, 06:58:35 am by Zog »
 

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #105 on: September 18, 2019, 09:52:05 am »
There's 2 mistakes: change the K to K1 (for the first set of coupled inductors; K2 for the second set; etc.), and change the RC filter on the current sense line to something like 100R and 220p because you generally want the time constant of the RC filter to be in the range of 0.5x to 2x the turn-on rise time of the switch.

EDIT - by not specifying K correctly the inductors weren't coupled, so you had a boost converter feeding into an LC filter and they really don't like that. Hence the ringing. In fact, in the real world the switch would be destroyed after the first switching cycle.

EDIT 2 - I did not check the rest of your circuit.
« Last Edit: September 18, 2019, 09:54:14 am by MagicSmoker »
 
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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #106 on: September 18, 2019, 10:33:48 am »
They are 2 separate inductors so the K1 trick did not work but putting K1 L1 L2 0 ie: not coupled produced this ! Like magic  :-+
Still singing a little on L2 though. But wayyy better.

Once again I have to thank you guys for helping me out here. It's actually more enjoyable learning this now than I thought it would be. Just a few LTSpice wrinkles to iron out. Like you can't use M for megohm apparently ?
Onwards and upwards I will be doing tank circuits soon .... yer right.


 

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #107 on: September 18, 2019, 11:15:59 am »
They are 2 separate inductors so the K1 trick did not work but putting K1 L1 L2 0 ie: not coupled produced this ! Like magic  :-+
Still singing a little on L2 though. But wayyy better.

Wait, whut?! The circuit in post 104 shows what should be a tapped boost, and in such the windings must be coupled tightly for it to work. You cannot take the output of the first boost inductor and have it feed directly into another (separate) inductor or the switch will be destroyed. So you really should have something like K1 L1 L2 0.995 (or 0.9975, which gives 1% and 0.5% leakage, respectively).

Like you can't use M for megohm apparently ?

Yep, one of the quirks of LTSpice and in defiance of almost everything else is that you have to use Meg to specify a million of something; M and m are interchangeably treated as milli, or a thousandth of something.
 
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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #108 on: September 18, 2019, 11:28:38 am »
This post ?
https://www.eevblog.com/forum/projects/design-of-smps-not-sure-what-these-spikes-are-being-caused-by/msg2696312/#msg2696312
You are right of course. I was forgetting everything I learnt about the tapped toroid I did before.
Too deep in spice and I "looks" like it is working so I throw the brain out.
To self, repeat after me. I need a transformer .... I need a transformer. :palm:

Well K1 did not produce any difference. That would of course explain my sudden output voltage drop.
 

Offline MagicSmoker

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #109 on: September 18, 2019, 02:36:54 pm »
...
To self, repeat after me. I need a transformer .... I need a transformer. :palm:

Well K1 did not produce any difference. That would of course explain my sudden output voltage drop.

So, there's a number of things wrong with 5.asc above which I have cleaned up and attached here as 5a.asc. It's not a complete design - this is my job and you ain't paying me, after all - but it should get you much closer to your (wacky) goal of powering a hundred Nixie tubes or whatever daft adventure you've set out yourself.

Note that I changed the following things:

1) Deleted extraneous specs from the input and output capacitors; first get a design working, then go back and add in ripple current and voltage ratings if you like (always include ESR, however, even if it's just a guess).

2) Added a gate resistor - always, always, always use a gate resistor when driving MOSFETs and IGBTs.

3) Changed the values on the RC filter for the current sense signal - note that this IC has a very low current sense threshold of 0.11V which makes filtering noise and spikes out of it even more critical.

4) Added an RC damper across the switch - you always need this with a tapped boost (or any configuration that has leakage inductance) - to eliminate much of the ringing. I did not optimize these values, but my guesses usually aren't too far off the mark. Usually you start with a C value that is twice the switch output capacitance then select R to be somewhere between 0.5x and 2x the characteristic impedance of the resonant network between the total capacitance and total stray inductance. Given that these parameters are sometime difficult to know ahead of time some guessing is inevitably involved. Note, also, that if the ratio of L1 to L2 is much different than 1:1 that it will become neccessary to use separate RC dampers across each inductor, rather than a single one across the switch, because the leakage inductances will be too different for one RC network to effectively damp.

5) Changed the transient simulation parameters - note that if you have to skip initial operating point in LTSpice to get a circuit to simulate, especially with one of their IC models, then something is probably wrong. It usually helps to specify the maximum timestep, however; something in the range of 0.1x to 0.5x the switching period usually ensures LTSpice doesn't inadvertently skip over ringing and other such phenomena.

6) Changed the feedback resistors to something more sensible which still gives Vout = 200V.

7) Changed the K1, L1 and L2 values to something more realistic for 300kHz CCM operation. Note that L2 has 3x as many turns as L1, so its inductance is 9x higher (inductance is proportional to turns squared). It wouldn't be unreasonable to go up to as high as 6x L1 for L2, though damping the ringing will become progressively more difficult as the turns ratio of the tapped boost increases farther away from 1:1.

8) Changed the output rectifier to the 600V SiC Schottky; this isn't strictly necessary, but sometimes a recalcitrant HV boost will behave better with this diode (as long as the average output current is <1A).

I didn't touch compensation though that almost certainly needs to be changed, and there are still some glitches in the MOSFET switching (doubled then skipped pulses - usually the result of noise on the current sense signal, though that looks pretty good at this point).
 
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Offline Zog

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #110 on: September 19, 2019, 09:39:19 am »
Quote
this is my job and you ain't paying me, after all - but it should get you much closer to your (wacky) goal of powering a hundred Nixie tubes or whatever daft adventure you've set out yourself.

No I am not paying you. But steady on now. "wacky, daft"? . Probably to some, but this project will bring me closer to world domination ! :box:
I am not really offended. You are right it is wacky and daft but I do have a serious plan for this.
Anyhoo... with that out of the way. Sniff sniff wipes tears away from eyes. :'(

Thank you for getting the thing in better shape. I still see that "ringing" in the waveforms but since it has passed your muster I guess it's acceptable "ringing". Possibly just an artifact of LTSpice ?

Quote
Usually you start with a C value that is twice the switch output capacitance then select R to be somewhere between 0.5x and 2x the characteristic impedance of the resonant network between the total capacitance and total stray inductance.

Gotcha, sorta. Thank you for that pointer. The C value is the easy part. The rest is experience and track layout but can always be tweaked later. I suspect you need very expensive equipment to do that properly though.

Quote
2) Added a gate resistor - always, always, always use a gate resistor when driving MOSFETs and IGBTs.
I swear to the SMPS gods that I will always add a gate resistor. Even if it's 1m \$\Omega\$. If I don't, may they take my first born, if they can suffer him. (kidding love the bugga).

Quote
5) Changed the transient simulation parameters - note that if you have to skip initial operating point in LTSpice to get a circuit to simulate, especially with one of their IC models, then something is probably wrong. It usually helps to specify the maximum timestep, however; something in the range of 0.1x to 0.5x the switching period usually ensures LTSpice doesn't inadvertently skip over ringing and other such phenomena.

I don't know why I use the skip the initial operating point. It worked either way but won't in future. Thank you for that tip about specifying the max timestep I had not even considered that and I will do that too in future.

Quote
7) Changed the K1, L1 and L2 values to something more realistic for 300kHz CCM operation. Note that L2 has 3x as many turns as L1, so its inductance is 9x higher (inductance is proportional to turns squared). It wouldn't be unreasonable to go up to as high as 6x L1 for L2, though damping the ringing will become progressively more difficult as the turns ratio of the tapped boost increases farther away from 1:1.

Yes get all confused about turns ratios being turns squared and larnt all I know from this video. But too thick to actually apply it in practice. :palm:

https://www.analog.com/en/education/education-library/videos/5579254291001.html

I am having a lot of trouble with magnetics in general. I mean the theory I learnt decades ago, but it still confuses me all the time. Getting old. (59).

I have been having more brainstorms. That are in the wacky category for sure.
Could one use a current transformer ? Probably not not closely coupled enough and huge leakage (guessing). But just thinking out loud here.
https://www.digikey.com/product-detail/en/pulse-electronics-power/PE-68383NL/PE-68383NL-ND/2265791
I like it because it's a tiny little bugger.

Moving on.
A proper transformer like this one.
https://media.digikey.com/pdf/Data%20Sheets/Wurth%20Electronics%20PDFs/750031353.pdf
Nice size, and probably what I should be hunting down.

Got hold of one of these from CoilCraft and this has got me stumped.
https://au.mouser.com/datasheet/2/597/da2032-463371.pdf


What sorcery is this. Each individual primary measures 10uH as per my LCR meter modified with kelvin clips at 100kHz. It's a good one not a piece of rubbish.
https://www.ebay.com.au/itm/DER-EE-DE-5000-High-Accuracy-Handheld-LCR-Meter-From-Japan-F-S/202765545258?hash=item2f35c4af2a:g:AAYAAOSwG-1ZxKJ0

Ok, fair enough but you can then put 3 of them in parallel and it still says 10uH ?. I did and it does. What ? wait ... err.. inductors in parallel are supposed to act like resistors. Not so according to the CoilCraft magnet gods.

Well if that's true. I am getting hold of a bunch of these to play with. I think these are the magic beans that will help me actually get a bit of flexibility so I don't have to remake a board every time.

https://www.coilcraft.com/pdfs/hexa-path.pdf
« Last Edit: September 19, 2019, 09:45:59 am by Zog »
 

Offline MagicSmoker

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #111 on: September 19, 2019, 11:22:35 am »
...
Thank you for getting the thing in better shape. I still see that "ringing" in the waveforms but since it has passed your muster I guess it's acceptable "ringing". Possibly just an artifact of LTSpice ?

No, the ringing is still a problem; I just got it better, not perfect. Tweaking the values of the snubber and even filtering the current sense signal more will be warranted, but I needed to leave some work for you to do, eh? Also, using a smaller FET (ie - higher on resistance/lower current rating) would help, as it will have a smaller output capacitance (Cjo in LTSpice).

That said, you're never going to eliminate all ringing in a hard-switched (that is, non-resonant) converter... Not without seriously degrading efficiency, anyway. And LTSpice does a really good job of getting such behavior correct - better than some professional SPICE packages with prices in the 5 digit range - so no, the ringing isn't just an artififact of the program, it really will occur (now, whether the ringing occurs at the exact frequency and amplitude depends on how accurate you were at determining all of the stray Ls and Cs).

Gotcha, sorta. Thank you for that pointer. The C value is the easy part. The rest is experience and track layout but can always be tweaked later. I suspect you need very expensive equipment to do that properly though.

Some empirical testing will likely be required, regardless, so just plan on trying a few different capacitor values on the prototype board. Snubber values are rarely critical (as evidenced by the frequent use of suspiciously generic values like 100pF + 10k or 10nF + 10R [seem familiar?], etc.)

I swear to the SMPS gods that I will always add a gate resistor. Even if it's 1m \$\Omega\$. If I don't, may they take my first born, if they can suffer him. (kidding love the bugga).

There are two reasons for the gate resistor: 1) it limits peak current charging/discharging the gate capacitance; 2) it suppresses ringing between that capacitance and stray wiring inductance.

Could one use a current transformer ? Probably not not closely coupled enough and huge leakage (guessing).

For measuring current, sure, though usually not worth the expense until the peak current is at least 10A or so and the sense signal is scaled to 1V peak.

Otherwise, yes, a proper transformer for L1/L2 would be better, but note that you can get pretty good results with a commercially available toroid with the right L2 value then adding the 1/3rd to 1/6th turns required for L1 on top of it as that will likely get leakage down into the 0.5% to 1% range. It's hard to do that well with any of the E cores (ETD, EFD, ER, EER, EC, etc.), actually.

EDIT  - forgot to add that the reason paralleled windings on a common core don't decrease in inductance is because they are all tightly coupled together. It's really no different than if the winding was made of multiple strands of insulated wire if you think about it. For the inductance to decrease in parallel - as happens with resistors - then you need the windings to be on separate cores with no interaction between them (that is, little to no mutual inductance).
« Last Edit: September 19, 2019, 11:24:42 am by MagicSmoker »
 

Offline Zog

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #112 on: September 19, 2019, 01:36:03 pm »
Quote
EDIT  - forgot to add that the reason paralleled windings on a common core don't decrease in inductance is because they are all tightly coupled together. It's really no different than if the winding was made of multiple strands of insulated wire if you think about it. For the inductance to decrease in parallel - as happens with resistors - then you need the windings to be on separate cores with no interaction between them (that is, little to no mutual inductance).

Ohhh. Ok thanks for clearing that up I thought the laws of physics had been changed while I was on the toilet.

Just going through cores on digikey.
This mob seem to have a material at the right sort of frequency so should not get too hot from core losses right ? https://www.ferroxcube.com/upload/media/product/file/MDS/3f3.pdf at least compared to plain old ferrite ?
I really would like a nice cool end result. As cool as possible anyway.

Digikey have this thing available.
https://www.digikey.com.au/products/en/magnetics-transformer-inductor-components/ferrite-cores/936?k=&pkeyword=&sv=1&v=1779&pv70=1069&sf=0&FV=1d480002%2C1f140000%2Cffe003a8&quantity=&ColumnSort=0&page=1&nstock=1&pageSize=500
Looks like it might be a bugger to wind though.
And they indicate inductance factor of 4.5uH So that is the max I will get out of it ?

I looked here but got a little lost.
http://www.encyclopedia-magnetica.com/doku.php/al_value

« Last Edit: September 19, 2019, 01:38:21 pm by Zog »
 

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #113 on: September 19, 2019, 04:31:32 pm »
AL is inductance per turn squared. If it says 4.5uH then a single turn will have an inductance of 4.5uH, 2 turns = 18uH, 3 turns = 40.5uH, etc.

Ferroxcube 3F3 (and TDK/EPCOS N87) are both excellent ferrites for 300kHz operation.

I ain't reviewing random cores, okay, but the pot core you pulled up is just about the worst choice possible, really.

Instead, look at part number 2100LL-180-H-RC on DigiKey which is an 18uH toroidal choke rated for 10.1A saturation current using a relatively low-loss material (Sendust). You could use the existing winding as the primary then wind on top of it, say, 4x as many turns, tying the start of the new winding to the end of the existing one to make a 1:4 autotransformer. Et voilla, a semi-custom tapped inductor for about $4 and a few minutes of your time. It will likely run hot and you'll have to restrict the peak current well below the claimed 10.1A saturation rating (maybe 5-6A peak), but it will be good enough to get something working and teach you a bit in the process.


 

Offline Zog

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #114 on: September 20, 2019, 02:37:49 am »
Quote
AL is inductance per turn squared. If it says 4.5uH then a single turn will have an inductance of 4.5uH, 2 turns = 18uH, 3 turns = 40.5uH, etc.
Great. That makes it easy.

Yes I am already using a "fairydust" core. They still run a bit hot for my liking but will play around with it some more till I get the inductance right then proceed to order a super pixie dust toroidal.

I have enough information now to ask my CoilCraft rep what he can do for me I think.
 

Offline Zog

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #115 on: September 21, 2019, 10:30:50 am »
Something is still bugging me.
All the datasheets mention Irms for their current ratings and not peak to peak.
Surely I should be following that advice and not be using peak to peak for inductor selection ? Right ?
 

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #116 on: September 21, 2019, 10:32:14 am »
Irms is a thermal rating only.

You're looking for saturation current, which should be greater or equal to the peak current used in circuit.

Tim
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Offline Zog

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #117 on: September 21, 2019, 10:34:02 am »
Ok. That's two of you now telling me. I will listen. Thank you. :-+

edit: one more quick question.
A 10uH to 1000uH is a 1:10 ratio right. I just need you guys to tell me that I am not a complete idiot.
« Last Edit: September 21, 2019, 10:43:40 am by Zog »
 

Offline MagicSmoker

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #118 on: September 21, 2019, 11:08:20 am »
Ok. That's two of you now telling me. I will listen. Thank you. :-+

edit: one more quick question.
A 10uH to 1000uH is a 1:10 ratio right. I just need you guys to tell me that I am not a complete idiot.

And you better pay close attention to the inductance at "rated saturation current" as it has typically fallen to 50% of the unbiased value, which is way lower than the usual definition of when "saturation" occurs (that is, by anyone besides commercial choke manufacturers), or a decline of 20% to, at most, 30%. Hence why I said you might want to limit peak current in a commercial choke to 50% of the saturation rating.

And yes, if one winding is 10uH and the other winding is 1000uH (1mH) then the turns ratio is 10 (either 1:10 or 10:1, depending on the direction).

EDIT - and no, not all the datasheets only mention RMS current; the part number I suggested before has Isat ratings, too.
« Last Edit: September 21, 2019, 11:10:33 am by MagicSmoker »
 
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Offline Zog

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #119 on: September 21, 2019, 11:34:28 am »
Great.
I realise that most mention Isat, but was a little confused.

Should I also include that huge inrush when it first starts up and getting to voltage as part of the selection process ? I am guessing yes. ie: I should take the peak to peak of the whole simulation and not just when it has settled down.

I am guessing yes because it's not working if it's saturated of course. But then again it's only for a few ms so is it that mission critical ?

edit:
Quote
as it has typically fallen to 50% of the unbiased value
better look up what that means.
« Last Edit: September 21, 2019, 11:36:03 am by Zog »
 

Offline MagicSmoker

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #120 on: September 21, 2019, 11:51:25 am »
...
Should I also include that huge inrush when it first starts up and getting to voltage as part of the selection process ? I am guessing yes. ie: I should take the peak to peak of the whole simulation and not just when it has settled down.

Yep. Inrush causing the boost choke to saturate is a major problem at higher power levels, but at this power level simply using the controller IC's soft-start function will deal with it.

Quote
as it has typically fallen to 50% of the unbiased value

better look up what that means.

Hmmm... I didn't think that was worded ambiguously. If you look at the datasheet for any of these commercial chokes* they will both state the inductance at zero current - ie, unbiased by DC - as well as the inductance at rated current or saturation or the like. In this part number I suggested earlier the unbiased inductance is 18uH, the rated current is 10.1A, but the inductance at that current has fallen to 8.5uH, or 47% of the unbiased value. This means that the real current rating isn't anywhere close to 10.1A.

* - a note on terminology: a choke is an inductor designed to tolerate DC bias without saturation.
 
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Offline Zog

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #121 on: September 21, 2019, 12:00:54 pm »
Sorry man. It's just that I am reading so much stuff it's kinda making my head spin.
Thank you for spelling it out for me. edit: better have a very close look at those curves.

Well. I have had a crack at making a 1:10 using this
https://au.mouser.com/datasheet/2/597/da2032-463371.pdf They do in all fairness to them say it is made for capacitor charging with a different chip. But I though I would try to see how it went.
Err... ugly. It's fine at say 20mA's or so .. but boy does it not like to draw a lot of current above that.

I bought one using the above inductor off ebay. Fine up to 40mA's but errr.. yer. After I blew it up I removed all the chips off and had a good look at the layout though, so all was not wasted. Very nice.


Attached for your amusement.

« Last Edit: September 21, 2019, 12:06:48 pm by Zog »
 

Offline MagicSmoker

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #122 on: September 21, 2019, 12:54:09 pm »
The DA2034 is a great little flyback transformer, but if that is what you are thinking of using then you might as well design a flyback rather than screw around with the tapped boost, dual/cascaded boost, etc.

Note that the dot ends of each winding in a flyback are inverted with respect to the other. E.g. - if the dot end of the primary is connected to the supply voltage then the non-dot end of the secondary goes to the output diode.

You can also use this transformer in the tapped boost by connecting the dot end of the primary to the 12V supply, the non-dot end of the primary to the dot end of the secondary, and the non-dot end of the secondary to the output rectifier. If you find the switch blowing up at a tiny fraction of expected power output then the most likely cause is that you've connected the dot end to the dot end (or the non-dot end to the non-dot end).

Also note that you need some kind of clamp across the primary to protect the switch in a flyback; the RCD type is preferred, but even a series fast diode + zener or TVS diode can work. If using the latter choose a zener/TVS voltage at least 50% higher than the reflected output voltage (which is the output voltage divided by the secondary:primary turns ratio; e.g. - 200V / (10:1) = 20V; set clamp voltage to 30V or higher).

This is probably a lot to digest, but I can't distill 20+ years of SMPS design into a few forum posts, even if you paid me.

 
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Offline Zog

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #123 on: September 21, 2019, 01:33:27 pm »
Thank you once again for your valuable tips.
I am designing a flyback at the moment with this.
https://www.coilcraft.com/pdfs/hexa-path.pdf
The flexibility is great and I am getting good results so far.
The snubber is noted. Though the application notes are a little confusing.

I am going for this one.


Not this one, if that even is a snubber.

 

Offline Zog

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #124 on: September 22, 2019, 08:07:20 am »
I think I might have something that works BUT. Now I am worried about wattages.
I should of course be using Average for this right ? Peak to peak is insane.

Another question too if I may. I am trying to get the model as close as I can and my datasheet mentions leakage and interwinding capacitance. Leakage I can do with the K factor but where do I put in the interwinding capacitance ?
In the primary or the secondary or both ?
https://au.mouser.com/datasheet/2/597/da2032-463371.pdf

P.S.
I am sure you guys know about this little magic bean. https://www.analog.com/media/en/technical-documentation/data-sheets/8304fa.pdf
200V right out of the box with no external mosfet.
Looks a little tricky to get right though and not enough amps for me. The application notes are an interesting read though all the same.

The transformer they recommend is right on the edge with the amps so I don't really know how they do it.

 

Offline T3sl4co1l

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #125 on: September 22, 2019, 09:08:42 am »
Put roughly half that capacitance across the secondary.  Or maybe more, it depends on the winding and it's not obvious from the datasheet.

Tim
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Offline Zog

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #126 on: September 22, 2019, 09:41:09 am »
Thanks Tim,
I just wacked the extra inductance in series with the primary too. I like easy.
Still lost on wattage though.
« Last Edit: September 22, 2019, 09:42:58 am by Zog »
 

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #127 on: September 22, 2019, 09:59:59 am »
I missed what wattage you're looking for?

Tim
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Offline Zog

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #128 on: September 22, 2019, 10:32:11 am »
I am looking at wattage through the inductors. Peak to peak through L1 (in blue) is about 96W but average is about 17W.
96W is kinda errr.. hot. The fet looks like it's in spec though. Roughly.


 

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #129 on: September 22, 2019, 12:17:31 pm »
That's instantaneous power and I think mostly reactive at that.  You need average power, with the DCR and core loss entered correctly.

Tim
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Offline Zog

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #130 on: September 22, 2019, 01:28:34 pm »
Sorry, you have lost me ? Reactive vs apparent ?
 

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #131 on: September 22, 2019, 06:41:02 pm »
Yes, those terms apply here, in the time domain, for pulse waveforms; it's not just for sine wave steady-state.  :)

Calculating those quantities exactly is a bit of a pain, but the short of it is: you're storing some energy in the inductor, then dumping it into the load.  This is reactive power.  Reactive power (VAR) divided by switching frequency (and there's a factor of 2pi in there) is the energy stored in the reactance, which is also E = 0.5 L Ipk^2.  (There'll be some factors of sqrt(2) or 3 or such in there, for a square wave, but the 2pi alone is correct for the sine wave case.)

Power dissipated in the inductor is VAR / Q, if you know the Q factor of the inductor.

Output power equals VAR if the current is discontinuous (i.e., all the inductor's energy is dumped into the load, every cycle, the current falling to zero inbetween).  If current is continuous however (if the switch is turning on while there's still current flowing to the output), output power goes up while VAR remains constant (VAR only depends on the change in current or voltage -- the ripple fraction; it's an AC thing only).

(This is handy when you consider a lossy core material that offers a lot of inductance at a low cost: if the power dissipation limit for the inductor is say 1W, and it has a Q of 10, you can get 10 VAR through it; that's only 10W output for a DCM converter, but 50 or 100W or more for a CCM converter with 20% or 10% or even lower ripple fraction, respectively -- assuming you can fit enough wire on the core to handle that much current, and assuming the core retains enough inductance under bias.)

Otherwise, you might as well calculate the losses in the resistive elements (DCR and core loss), or treat it as a black box (fairly necessary for general SPICE models) and wire a power meter circuit around it.

Tim
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Offline Zog

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Re: Design of SMPS - Not sure what these spikes are being caused by.
« Reply #132 on: September 23, 2019, 09:03:38 am »
Think it's time to just build and start cooking toast.
Going for flyback with the 10u/1m inductor. Will put more holes in to test out others if it starts melting.
 


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