Hi Zog,
As was discussed, your vin = 12v, vout = 220v and pout = 100w. Your chosen topology is the tapped boost.
One problem for the tapped boost with such high “primary” current (around 14A peak in your case) is that unless you can ensure very tight coupling between the two sections of the tapped inductor, then you are going to get high voltage spikes on the drain of the fet whenever it turns off. I think you may need (depending on your actual coupling) to put a clamp across the primary side of the tapped inductor as in the attached. The bare basic schematic is attached…also the LTspice simulation. This is a free download simulator and you will find it very easy to use.
Just open the simulation (.asc file) and hit the running man icon….then click away at your leisure to see the circuit voltages and currents…ALT, Left click to see the power…….its a lot easier than that TI webbench one.
Its always best to run some kind of representative simulation of a SMPS first before going to the bench. If an SMPS works on the simulator, then it doesn’t mean it will work on the bench, but generally, if you cant get some kind of representative simulation working first, then its often a waste of time going to the bench. All the best SMPS engineers ive worked with at places like Alcatel, Tridonic, etc etc are avid users of simulators…….if only just to check over what you are about to do on the bench.
I think a tapped boost inductor at the current levels here, would preferably need to be interleave wound to increase coupling….otherwise I suppose you can just have a chunky clamp resistor and just eat up the leakage energy like that.
Your vin is only 12v, and your peak fet current is going to be in the region of 14A or so…….so you will need a fet with low rds(on)….but also, if you are getting high voltage drain spikes due to the leakage inductance, then you will need the fet to be rated to that high voltage….the problem is that low rds(on) fets are often not available with high voltage ratings.
Anyway, if you dont use a fet with low enough rds(on), then you are just not going to get enough power throughput, as the volt drop in a high rds(on) would mean your effective input voltage is even lower than 12v.......this would get worse as the fet warms up and its rds(on) increases.
One of your schems shown here shows a fet with 3 ohms rds(on), and thats the min value.....you wont be able to get much current through that from a 12v input.
This is one of the reasons doing a sim first is good.,...it flags up points like that which are so easy to forget.
This is why I believe that the Dual Boost converter is better for you, and I have provided details in a following post. In the Dual boost converter…the fet that sees the higher current only sees a low voltage, and so you can easily find suitable fets. Also, the Dual Boost doesn’t have coupled coils, so leakage inductance does not have to be dealt with.
Leakage inductance isn’t too bad when not much current flows in it…because the energy of the leakage inductance is i^2.R. But with your high-ish peak current, you could end up with high leakage energy to dissipate….depending on how well coupled are your coils.
Even with a tapped boost, the high step up ratio is likely to mean that you will need slope compensation. If you pick a constant off time controller then you won’t need to use slope compensation.