Did You Hear of Such an AM Receiver? For DSB-Suppressed Carrier.

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What I presented on post #9 is just about a new DSB-SC demodulator, nothing else. And if someone has LTspice he can set the parameter:
FM_pk = 0 instead of 0.5
By doing this, he removes the FM modulation completely while the recovered AM audio signal stays the same. For instance, in this case, the DSB-SC demodulators of Costas Loop and Squaring method (which are more complex to build than mine) can also recover it.

The problem here is that I'm using Linux OS on aarch64 platform, while LTspice is for Windows/Apple OS with x86/x64 platform. So, I have no way to test it, because I cannot run LTspice. And it's hard to see the root of your idea from schematic.

This is why I asked to write it in math for matlab/octave, so that it can run on any OS/platform. Or at least describe it using math with usual text description.

As you know AI bots are made by humans. So, if a programmer has no idea about something, his AI bot cannot know it too.

That's not technically correct.
Here is response from AI bot on your statement:

Your statement is partially true, but it simplifies how AI works. AI bots are trained on vast amounts of data, including information that the individual programmers may not personally know. While programmers build the systems and define their structure, the knowledge embedded in AI models comes from the data they're trained on, not solely from the programmers' understanding.

So, an AI bot might "know" things that its creators are unaware of, as long as that knowledge exists in the training data. However, if the data lacks certain information, the AI won’t have it either, regardless of the programmers’ expertise.

In other words, AI's knowledge is practically independent of the programmer's knowledge, just as the information written on a piece of paper does not depend on the knowledge of the person who made the paper.

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I guess for example, this is one of the questions that an AI bot cannot answer properly:

BW_am is the bandwidth of an RF channel when the amplitude of its carrier is modulated.

BW_fm is the bandwidth of the same RF channel but when the frequency of its carrier is modulated.

The question is:
What is the bandwidth, BW_am_fm (in function of BW_am and BW_fm), of this channel when both the amplitude and frequency of its carrier are modulated at the same time?

I wish to know how an AI bot will answer this question. Unfortunately, unlike most readers here, I can’t access one.

Here is the answer on your question from Chat-GPT:

When both amplitude modulation (AM) and frequency modulation (FM) are applied to the same carrier, the resulting bandwidth BW_{am_fm} will generally be the sum of the bandwidths required for each modulation independently, as both forms of modulation add spectral components to the signal.

Thus, the bandwidth for the combined modulation can be expressed as:

BW_{am_fm} = BW_am + BW_fm

Explanation:
- BW_am​: This represents the bandwidth required for the AM signal. For a standard AM signal, this bandwidth is twice the highest frequency present in the modulating signal.
- BW_fm​: This represents the bandwidth required for the FM signal. It depends on both the frequency deviation and the highest frequency of the modulating signal, typically calculated using Carson's rule.

When both modulations are applied simultaneously, the spectral content of the signal includes components from both types of modulation, leading to the combined bandwidth.

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I also asked Chat-GPT to analyze your schematic from picture in this post: https://www.eevblog.com/forum/projects/did-you-hear-of-such-an-am-receiver/msg5770781/#msg5770781

And here is Chat-GPT result:

> Analyze schematic for DSB signal demodulation from picture in attachment

The circuit represents a combined demodulator for DSB-SC (Double Sideband Suppressed Carrier) and FM (Frequency Modulation) signals using a Phase-Locked Loop (PLL). Here's an analysis of the key components:

1. Input Signal:
    The input signal is modulated in both amplitude (AM) and frequency (FM).
    Variables V_AM and V_FM​ simulate the AM and FM modulated signals, respectively.

2. DSB-SC Section:
    The DSB-SC signal is introduced into the circuit via the DSB - SC + component.
    Logic gates (74HC86) are used to process and recover the original DSB-SC signal.

3. FM Section:
    The FM signal is generated using the SINE() function for frequency modulation.
    A PLL, implemented with CD4046 and 74HC86, is employed to extract the frequency-modulated information.

4. Signal Processing:
    Limiters and logic gates (74HC86) prepare the signal before it enters the PLL for demodulation.
    The "Optional" section includes additional circuitry for muting (Mute) using the CD4066 component.

5. Demodulation:
    The CD4046 component is used for phase detection and retrieval of the FM-modulated signal.
    The DSB-SC signal is processed separately through its own signal path.

6. Output Signal:
    The outputs, R_{AF_FM}​ and R_{AF_AM}​, correspond to the recovered FM and AM signals, respectively.
    These outputs can be connected to an analyzer or an amplifier for further processing.

Remarks:
- This circuit effectively demonstrates the integration of AM and FM signal processing in a single design.
- The PLL (CD4046) is utilized efficiently for FM demodulation.
- However, the accuracy of demodulation depends on proper tuning of parameters such as F_lock​, F_PLL​, and the input signal characteristics (amplitude, frequency).

Let me know if you have any specific questions or need further clarification!

Then I asked to analyze DSB-SC demodulation signal path. Here is result:

> Analyze DSB-SC demodulation signal path

The DSB-SC (Double Sideband Suppressed Carrier) demodulation signal path in the provided circuit can be analyzed as follows:

1. Input Signal (DSB-SC):
    The DSB-SC signal is introduced into the circuit via node DSB-SC+.
    The signal is represented as V=V(Fc)⋅V(AF), where Fc​ is the carrier frequency and V(AF) is the amplitude-modulated information.

2. Signal Limiting:
    Limiter (U1):
        The input DSB-SC signal passes through a limiter (constructed using a 74HC86 XOR gate) to clip the signal and remove amplitude variations.
        This step ensures the signal is prepared for zero-crossing detection and phase processing, emphasizing the frequency and phase information.
        Resistors R3, R8, and capacitor C1 set the operating conditions for the limiter stage.

3. Signal Delay and Phase Adjustment:
    Delay Circuit (U2):
        The output of the first limiter is passed through another XOR gate (74HC86) with a delay introduced by R2, C2, and R11, C7.
        The delay helps align the signal for proper phase detection and demodulation.
        This block ensures synchronization of the DSB-SC signal for downstream processing.

4. Phase Detection:
    The delayed and limited signal is processed through another XOR gate (U2) for phase detection.
    The result of the XOR operation helps distinguish the suppressed carrier and the amplitude-modulated components.

5. PLL Demodulation (Optional Path):
    PLL (CD4046):
        While primarily used for FM demodulation, the PLL can also lock onto the carrier frequency of the DSB-SC signal.
        The recovered carrier frequency can assist in reconstructing the original amplitude-modulated signal.

6. Output Signal Recovery:
    After phase detection and XOR processing, the demodulated DSB-SC signal is passed through a low-pass filter (outside the XOR logic path).
    The low-pass filter removes high-frequency components, isolating the baseband signal V(AF), which contains the original modulating information.
    The final output is available at R_{AF_AM}​, representing the recovered AM signal.

Key Observations:
1.    The demodulation relies heavily on logic gates and limiters for phase detection.
2.    The XOR gates (74HC86) are critical for detecting phase differences and reconstructing the suppressed carrier.
3.    The low-pass filter ensures only the baseband signal is retrieved at the output.
4.    For accurate demodulation, the system depends on proper synchronization and delay adjustments.

Let me know if you need a deeper analysis or specific parameter details!

As you can see, it just extract basic information

[KerimF]

As you can see, it just extract basic information

First, thank you for your time to ask Chat-GPT because I can't do it.
It is sad that you cannot test the circuit. Those who can run LTspice they may be able to update it too.

So, I will try to explain it verbally.
The reason that a conventional PLL topology cannot lock in case of DSB-SC (and if m>1), is that the carrier phase shifts 180 degrees every time the modulating signal cross 0V. So, if the two inputs of its comparator are of the same frequency fc, the polarity of the comparator output will change at every zero crossing too and this prevents the PLL to lock.

To avoid this situation, I simply doubled the frequencies at the comparator inputs.

[1] On the schematic, R2/C2 and R11/C7 delayed the XOR output U1, V(LMT). Their total delay is 90 degrees, that is equal to Tc/4 [550 ns, in case fc=455 kHz). At the output of XOR U4, V(DBL), we get a square wave whose frequency is 2*fc.
[2] The mid-frequency of the VCO is also set to 2*fc.

Now, the polarity of the comparator output doesn't change because at zero crossings V(DBL) stays/looks the same despite the reversal phase of the suppressed carrier.

Naturally, the VCO output (2fc) has to be divided by 2 (see U3).
And the total delay of the XOR U5 (90 degrees of fc) and the R7/C5 is added and adjusted to let CD4066 be in phase with the suppressed carrier.

Hope this helps.

[KerimF]

I think the readers who had the time to analyze and understand the demodulator presented here (which could be called ‘Kerim Loop’ or ‘Harmonic Loop’) are shy to add two negative comments/remarks about it:

[1] You said it can recover, at the same time, two independent signals which modulated the amplitude and the frequency of the suppressed carrier, respectively. But when the AM modulating signal is off (silence periods during a conversation), the FM recovered signal will be lost (the two sidebands are off, no RF signal).   

[2] You said R7/C5 (delay circuit) is added and adjusted to let the synchronous detection (by CD4066) be in phase with the suppressed carrier. This works if the frequency of the suppressed carrier is fixed. In case its frequency varies, its phase varies too, forwards and backwards. The gain of the synchronous detector decreases in both directions which results to a gain distortion.

For case [1], in a real application, this is can be solved in a way that suits the purpose of adding a second signal as FM.
For case [2], the fixed delay needs to be controlled by the average voltage of VCO_in (LPF output) in order to follow the phase variation. In a real application, the gain distortion (when FM is also used, as in the example on reply #9) is relatively small and not noticed during a conversation. But I am working on it to make it a voltage-controlled delay circuit (VCD).

Cheers,
Kerim