DRV2700 HV piezo driver problem [SOLVED]

[Unixon]

I have a project with DRV2700 high voltage piezo driver in flyback configuration.
The problem is that the output voltage never exceeds about 65-78V when driven above that level (can reach 77-78V shortly but then slowly degrades to 65-66V).
Output voltage degradation depends on temperature, I could get 10-20V increase by freezing board around driver and transformer (but DRV2700 on that board eventually died).
High side Vpp after transformer before rectifier is about 110V, current consumption is 1.8W with no load.
Transformer is exactly the same as in demo board DRV2700EVM-HV500.
Feedback circuit works fine, voltage is well controlled in 0-65V range, H-Bridge works fine and consumes about 0.6-1mA in gate protection circuits.
Discharge circuit with Q2 is not involved in current consumption as Q2 is closed.

Related parts of schematics and board layout are in attachment.

Any ideas on what's wrong?

[duak]

Does the DRV2700 get very warm?  Perhaps it is internally overheating and limiting current.

Does transformer T1 get very warm?  The resistance of the windings may increase enough to reduce the voltage at higher output currents.

[hv222]

Is transformer soldered properly - pin 1 in right place? Can you share oscillograms of signal at SW pin?

[Unixon]

Does the DRV2700 get very warm?  Perhaps it is internally overheating and limiting current.

Not enough warm to fail finger test, but may be warmer than it should.
I need to get to my IR thermometer or a thermocouple to tell temperature precisely.

Does transformer T1 get very warm?  The resistance of the windings may increase enough to reduce the voltage at higher output currents.

I think it does gets warm, because cooling this piece of board by touching with a fingertip or blowing air over causes up to 10V increase in output voltage.

[Unixon]

Is transformer soldered properly - pin 1 in right place?

Yes, I compared my assembled boards with TI's board and design and they do match transformer orientation.

Can you share oscillograms of signal at SW pin?

Yes, sure, this will take a little time. One thing I can tell right away - they seem very suspicious - too close to meander.
I think I'm running into overcurrent/saturation here, but why TI's board doesn't with exactly same values in circuitry?
Unfortunately, I don't have the original demo board to measure reference voltages/oscillograms.

[Unixon]

Here's SW node when DRV2700 told to produce 100V, but it does only 62V.
This is output of secondary before rectifier.

[hv222]

Yes, sure, this will take a little time. One thing I can tell right away - they seem very suspicious - too close to meander.
I think I'm running into overcurrent/saturation here, but why TI's board doesn't with exactly same values in circuitry?
Unfortunately, I don't have the original demo board to measure reference voltages/oscillograms.

Check REXT resistor. Is responsible for current limit. Maybe is damaged or have bad solder joint. What is feedback voltage, when you set output to maximum value? If feedback voltage is close to 1.3V then check again feedback circuit and R38/C37. If it's below check around Q2. Maybe discharging circuit is on all time.

[hv222]

Check again flyback transformer position. SW pin voltage looks too high. Maximum value of SW voltage (excluded oscillations) should be VDD + Vout/turn ration that mean 5V + 100V/10 = 15V. You have much more here.

[Unixon]

Check again flyback transformer position. SW pin voltage looks too high. Maximum value of SW voltage (excluded oscillations) should be VDD + Vout/turn ration that mean 5V + 100V/10 = 15V. You have much more here.

Oh, sh*. I've measure the wrong thing. This is not SW node, this is output of secondary.

[hv222]

That explains negative values of voltage here 

[Unixon]

That explains negative values of voltage here 

OK, here's correct shots of SW node at Vout set to 10V, 50V and 100V. At 100V actual Vout is degraded to 63V.

[Unixon]

Check REXT resistor. Is responsible for current limit. Maybe is damaged or have bad solder joint.

No, it's OK. I've changed that to several values in allowed range.
By default I put there 10k as in demo board, I've also tried 7.5k as a minimum value (max. current) and 30k as max. value (min. current).
With Rext=30k Vout becomes limited at 16-17V, with 7.5k vs. default 10k Vout is probably raises a bit, but I can't say that definitely.

What is feedback voltage, when you set output to maximum value? If feedback voltage is close to 1.3V then check again feedback circuit and R38/C37. If it's below check around Q2. Maybe discharging circuit is on all time.

When Vout is below desired value, Vfb is also below Vref, it could be anywhere down to zero, 0.4-0.5V for example. But Q2 is closed at that time!

[Unixon]

I think I found the problem. After all, it was the excessive loading by the H-bridge MOSFETS.
When H-bridge is enabled and low side is turned on, due to resistor ratios high side also gets turned on and I observe a short across safeguard 1k resistor.

[Unixon]

I suppose this mod should fix the problem... But then I will have to re-spin the board, even at best pads selection this may not look very nice on existing boards.

[Unixon]

OK, now this works fine. So it wasn't a DRV2700 problem, my schematics for H-bridge was insufficient.

Thanks everyone, problem solved.

[NiHaoMike]

Simpler solution to try: remove the 100k resistors, then remove and bypass the driver transistors so the logic signal directly drives the low side output MOSFETs. Then put the 100k resistors so that when one side of the bridge is pulled low, the other side is pulled high.

[Unixon]

Simpler solution to try: remove the 100k resistors, then remove and bypass the driver transistors so the logic signal directly drives the low side output MOSFETs. Then put the 100k resistors so that when one side of the bridge is pulled low, the other side is pulled high.

Did I get it right that your suggestion is to use low side MOSFETs to drive both load and high side MOSFETs? I know this configuration but I have to think about its applicability.
The bridge works at potentially high voltage (150V max operational by design, MOSFETs are 250V rated), so I have to both protect gates and keep channels wide open when enabled so they are intentionally driven to saturation (+/-15Vgs) whenever possible. Also I want an additional layer of isolation from between output stage and MCU so that in a fault condition they only fry themselves but not the entire board.