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DIP version of voltage level converter SN74LVC1T45 ?

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FrankBuss:

--- Quote from: OM222O on April 11, 2019, 12:34:38 am ---in terms of your 3v regulations, I'm not sure what you are using that will be so poorly regulated that some switching can cause spikes ... even then, that's exactly what decoupling capacitors are used for?
In case there is a misunderstanding, I meant 1k resistor on the inputs, not the supply rail itself!

--- End quote ---

All linear regulators I know do only regulate the voltage down, like a variable series resistor. The resistance can't get negative, so if you add some voltage on the 3.3V side, the voltage at the decoupling capacitor would rise through the zener clamp diode of the flash, the faster the lower the capacitor. It might not destroy the flash or FRAM with a 1k resistor with only 5 mA, but nevertheless it would be out of spec.


--- Quote from: OM222O on April 11, 2019, 12:34:38 am ---Edit: these 3 channels work in parallel and propagation delays are the same regardless of the input singal, so clock is inverted with the same delay as data line (within the specified tolerances that is) so there is not much phase shift, if any! I'm not sure why you would use 2 gates for clock and one for MISO/MOSI? that is actually a use case which can cause issues. just use the same number of gates for all signals.

--- End quote ---

I need to invert clock twice, because regardless of the SPI mode, it is sampled and changed at the same edge at the sender and receiver. E.g. if I use SPI mode 0, the data is changed at rising edge, both MISO and MOSI, and it is sampled at falling edge. If I would invert the clock only once, it wouldn't work, unless you rely on a minimum gate propagation delay, but this would be a bad design. But for MISO and MOSI you would need just one gate, because this is easy to change in software in the transfer function.

OM222O:
well it seems everyone hates this solution, but I emphasize again: it has worked without any issues in dozens of designs. even if you look at the functional diagram of voltage converter ICs, many of them use this exact same thing, just embedded as one chip on the silicon. for example: http://www.ti.com/lit/ds/symlink/cd4504b.pdf


It is by no means poorly designed, too slow or bad on supply regulations. I will not fight anymore, but I highly recommend you try it with 1k resistors on the inputs for current limiting. you will be surprised as to how well it works. I don't have access to my uni lab right now, but in our design projects this has been used for the past 3 years or so in most of our projects without a single hiccup  :-//

edit: I'm not sure the input resistance on the inputs (didn't look carefully enough) but you might not even need the 1k resistors if they are already included on the inverter chips (which they most definetly are, because you can connect them back to back without an issue, 5v vs 3.3 is also not big enough to exceed 20mA per pin!)

FrankBuss:
Well, it looks like it is working, but the datasheet doesn't allow higher voltages at the input, and unless you have a written note from the manufacturer that you can do this, I wouldn't do it. And did you test it with 20 MHz, or at 85°C? I think it would be too slow. And as oPossum wrote, the series resistor smooths the edges of the input signal, which introduces additional delays and possible problems.

These flash chips can be really picky. I did a test with one:

https://hackaday.io/page/6060-spi-flash-test

and just using a resistor divider for the 5 V to 3.3 V translation didn't work, even with a slow 1 MHz clock, because the flash chip expected a faster rising and falling time on the clock line, otherwise it didn't work reliable. I guess the reason is because it can run with up to 104 MHz according to the datasheet, and looks like it doesn't have a schmitt trigger input, so this might result in bad behavior for slow edges.

T3sl4co1l:
You mean the series resistors?  Nah, the level shifter circuit is full CMOS -- resistors would cost supply consumption, which would be specified.

Relying on input protection diodes is a bad idea for three reasons:
1. They're intended for transient use only.  This isn't always relevant, but sometimes it is.
2. The charge injection can disturb logic states, or affect propagation time, etc.
3. The injected charge returns through the substrate and nearby ESD diodes, depending on which ones are active.  This increases supply consumption considerably, and can interfere with signals on nearby pins.

I've written a model for this before.  It was the CD4001, including measured hFE of the "ESD diodes" that are actually BJTs.  The input-to-VDD diodes actually shunt about half of the positive ESD current to ground (the current is cascoded through a PNP with low hFE).  A small fraction (about 3%) leaks out adjacent input pins if applicable (ESD diodes are typically per-gate, so in a 4001, this causes leakage out the other input pin, but doesn't affect other gates; this is N/A for a buffer/inverter).  The VSS-to-input diodes work the same way but have good hFE, so essentially all the negative ESD current is drawn from VDD.

Anyway, this is easily avoided, by adding external schottky diodes (BAT54C seems a likely choice), or using a device with an input structure that tolerates higher voltages (like the CD4504 pictured).

I don't think discrete logic has any problems with #1, so that should be safe.  It is something to be aware of, in general.  For instance, FPGAs can have these limitations.  Many are made with input structures as small as possible -- to offer as much speed as possible, given the wide range of output types they need to be programmable for.  Consequently, they can't handle much DC current.  This is a reliability problem, driven by electromigration.  Some specify transient voltage or current limits, others don't.  (Offhand, Altera's Cyclone III was rated for VCC + 1V or VDD - 1V, for 2ns, or something like that, and 2mA DC.)

Tim

OM222O:
external diodes will be costly. the point of this circuit is being dirt cheap and from jelly bean parts. Yes, you can absolutely design something over the top "which is better in x and y and z" but do you really need that for level conversion? if it works for your application, well then it does. if you go with that mindset, a simple ADC circuit cane either be made with current limiting resistors + some filters costing about 5$, or adding a bunch of protection and whatnot, making it cost 20$ ...

As I mentioned you would probably be fine without any external resistors and you will not shorten the life of the chip. it's extremely unlikely that micro can even put out that much current at 5v to a logic chip. I have not tested at 85C or 20MHz ... the logic part of the circuit shouldn't get hot, so just test at ambient. as for the frequency, the data sheet suggest it should have no problem, but you can test with your oscilloscope and a signal gen (micro at the clock speed you want) just to be sure. in terms of reliability, I have had no issues with this design if you pick a fast enough chip, which you can choose different logic families for that. I think S series are more power hungry but are faster because they use schottkies. it only needs to be a hex inverter chip from the family you want.

Edit: voltage on the inputs does not matter at all. there is no specification on it whatsoever. only maximum current rating which is +-20mA. keep that in mind.
in terms of note from manufacturer look at page 9:



if you just read the datasheets of the exact chip from the family you want, 99.9% of your questions are already mentioned there

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