Discrete CPU build: logic type, architecture...?

[Martinn]

Hi,

I really was impressed when I read the IBM System/360 story - building a mainframe computer (with floating point and all) based on discrete components (packaged in their SLT modules) and now the idea is - how could I build a discrete CPU? I am aware of MT15, Megaprocessor or Monster6502 and of course just duplicating one of those would not be fun. So I'm looking for comments/ideas here - some random thoughts:

• I'm not a fan of manual soldering or wiring. The idea would be to design a PCB (KiCad) and have it made with the smallest discrete components JLCPCB offers (seems to be 0402 passives and SOT-723 transistors)
• The HP-35 calculator has a serial (1 bit) CPU - maybe build something like this? However, debugging is nasty as you always have to decode a serial bitstream.
• What logic type would one use? I really like the NMOS style of the 6502 with heavy use of transmission gates (problem being that there are no single/cheap transmission gate capable discrete transistors)
• Maybe RTL? Some nice ideas about the RTL and CDC6600 here https://cpldcpu.wordpress.com/2020/02/14/what-made-the-cdc6600-fast/
• I once did a small CPU in an FPGA for data preprocessing and the trickiest thing (timing wise) were the large multiplexers (particularly using 4 input LUTs). So wiring many sources together seems helpful - like with n-input RTL NOR or using transmission gates.
• The smallest "computer" one could build out of such a CPU would be a "pocket calculator" - maybe not as sophisticated as the HP-35, as they put tons of numerical tricks in their software to make it work given the available ROM space
• I guess that anything of that complexity will never work without having a full functional simulation. So I guess some workflow linking gate level description, simulation (maybe via VHDL) and schematic netlist (KiCad) will be necessary (sigh). However, VHDL modeling of bidirectional transmission-gate circuits seems...? So the bag of dirty discrete tricks probably has to be limited to what can easily be simulated.

Any ideas? Thanks!

Martin

[MrLau]

For the layout/sim workflow I highly recommend checking out this guys project
https://hackaday.io/project/180839/logs

It's really interesting and also made me seriously consider doing a discrete CPU, probably writing some of the place and route and layout tools myself.

[rstofer]

I first used a real computer in 1970 - an IBM 1130  (see ibm1130.org).  At one point I decided to build a TTL version of the machine (around 1974) and I decided to use a microcode approach with blown-link PROMs for the microcode store.  I didn't finish it because static memory just wasn't available at the hobby level.  The 2102 RAM didn't hit the hobby level for a couple of years and I had already bought the Altair 8800.

Fast forward to around 2003 when I retired and I built the entire 1130 and all of it's peripherals in a modest FPGA.  I can now run the entire factory code without change.  I even implemented a LaserJet version of the 1627 plotter.  There is no concept of floating point hardware, there never was on this machine.  Sample of plotter output attached.

These days I think the LC-3 RISC CPU is a really nice project for an FPGA.  It too lacks floating point, many small CPUs do the same.
https://www.eevblog.com/forum/fpga/alu-in-mips/msg3698950/#msg3698950

At a bare minimum, the Blue computer in "Computer Architecture" by Caxton C Foster is interesting.  It is a minimal computer that might have sold for a few thousand dollars back around 1970.  Maybe upgrade to Indigo in the following chapter - it adds index registers.

https://www.alibris.com/Computer-Architecture-Caxton-C-Foster/book/1255656

I have the 2d edition and it is just $5.59 at the above link

Ben Eater's project deserves notice, it's pretty slick.

https://eater.net/8bit/

If you are building a CPU from scratch with discrete logic, I highly recommend using a microcode approach.  You might pursue AMDASM to see how a microcode assembler works.  I doubt that the assembler itself is available but it might not be hard to write one in Python.

BTW, the LC-3 project, as described by the authors, uses a microcode approach.  I used a large Finite State Machine instead.  There is also an LC-3b project which uses byte addressing instead of word addressing.

[Benta]

If you're into 1-bit designs, the Motorola MC14500 might interest you:
https://en.wikichip.org/w/images/3/3e/Motorola_MC14500B_Industial_Control_Unit_Handbook.pdf

[rstofer]

It's the 50th anniversary of the Intel 4004 and there is plenty of info on the web.  It was a 4 bit chip designed for use in calculators.  It led to the 8008 and the 8080.  The 8086 and 8088 were next up (the 8085 came along somewhere around here, it was a great chip) and we were off to the races.

[jmelson]

Building a discrete transistor computer is a very big project!  There are some hobby-level digital clock projects that have been put online to give you some ideas on packaging technology.  But, even a very simple CPU is going to be about 5-10X more logic than a clock.
SOT-23 transistors are fairly easy to work with, but FFs are pretty complicated.  In the IBM 360, they used D-latches to avoid full-on flip-flops.  Each SLT module had a dual 2-input gate. Two of these gates could be cross-connected to form the storage element, and another two could form the input gating.  So, a single D-latch could be built from 2.5 SLT modules. (it needs a gate wired as an inverter so it can feed D and D/ into the input gates.)  Building a CPU with D-latches requires multiple clock phases.

You could probably make gates with SOT-23 transistors a bit smaller than the old IBM SLT technology.  And, I think IBM made a mistake with the 360.  They were in the mindset coming from the earlier SMS technology to put multiple identical basic functions (like inverter or gates) on a card.  it might have made a lot better sense to put major functions on slightly larger cards, such as a one-bit slice of an ALU or something like that.
Jon

[David Hess]

What logic type would one use? I really like the NMOS style of the 6502 with heavy use of transmission gates (problem being that there are no single/cheap transmission gate capable discrete transistors)

Maybe RTL? Some nice ideas about the RTL and CDC6600 here https://cpldcpu.wordpress.com/2020/02/14/what-made-the-cdc6600-fast/

I would use a discrete version of integrated injection logic with bipolar transistors.

[Martinn]

SOT-23: I really don't want to use such large components. I have soldered enough SMT for a lifetime, now it's time to let some P&P machine do that job. Just checked again and JLCPCB now has SOT-723 MOSFETs and 0201 resistors. Put together a simple D-Latch:

7 transistors... Assuming a handful 8 bit registers like ACC, X, Y, PCL, PCH, SP, Instr.-Reg, AL, AH (6502 style) would give 8x9x7 = 504 transistors for the data path storage.  In layout

30 mm^2, so on a 200x200 mm PCB around 1300 latches total. At least the right order of magnitude.

[Martinn]

I would use a discrete version of integrated injection logic with bipolar transistors.

Interesting, never heard of this before. Would you not be considered about varying V-BE and gain? Would component count actually be lower? Component cost is not an issue, a MOSFET is < $.02.

[Martinn]

For the layout/sim workflow I highly recommend checking out this guys project
https://hackaday.io/project/180839/logs

It's really interesting and also made me seriously consider doing a discrete CPU, probably writing some of the place and route and layout tools myself.

Very interesting! And quite close to what I had in mind... maybe too close?
I wouldn't build a discrete gate level library for the synthesizer (wouldn't know how), I would just design building blocks (like the D latch), write a matching VHDL behavioral model and build up from there.
Also nice idea with the optimized automatic placement!

[David Hess]

I would use a discrete version of integrated injection logic with bipolar transistors.

Interesting, never heard of this before. Would you not be considered about varying V-BE and gain? Would component count actually be lower? Component cost is not an issue, a MOSFET is < $.02.

Where matching is required, emitter ballasting with a resistor in series with the emitter takes care of it.  Of course this means more parts.

[jmelson]

A much simpler FF is the diode-steered, capacitor clocked FF design from decades ago. I bulit one of these when I was about 16, but didn't have the test gear to tell if it worked.  I recently simulated it and built it up on a wireless breadboard, and demonstrated that it worked quite well.  I can't seem to find the schematic I used for the sim, but here's a link to a capacitor-triggered FF.  It is the next to last schematic on that page.
<https://www.google.com/url?sa=i&url=https%3A%2F%2Fwww.nutsvolts.com%2Fmagazine%2Farticle%2Fbipolar_transistor_cookbook_part_6&psig=AOvVaw3KlXK2nD_eLFKNokJcQE-q&ust=1637945057166000&source=images&cd=vfe&ved=0CAsQjRxqFwoTCKDmpP36s_QCFQAAAAAdAAAAABAP>

Jon

[jmelson]

Here's another, like the circuit I built:
https://www.google.com/url?sa=i&url=https%3A%2F%2Fwiki.analog.com%2Funiversity%2Fcourses%2Felectronics%2Felectronics-lab-24&psig=AOvVaw2G77HA_YKVtUU_4hO4A47H&ust=1637947128147000&source=images&cd=vfe&ved=0CAsQjRxqFwoTCNjn9tqCtPQCFQAAAAAdAAAAABAD

Under D type FF, it uses one more transistor to give D and D/, and then only 2 transistors for the FF, but a few additional diodes, resistors and caps, but those can be REALLY small today.  Modern fast transistors can make this FF run pretty fast.

Jon

[Martinn]

Here's another, like the circuit I built:
https://wiki.analog.com/university/courses/electronics/electronics-lab-24
Under D type FF, it uses one more transistor to give D and D/, and then only 2 transistors for the FF, but a few additional diodes, resistors and caps, but those can be REALLY small today.  Modern fast transistors can make this FF run pretty fast.
Jon

Hi Jon,

I don't like this style too much:

• 17 components! I plan to use SOT-723 transistors and 0201 resistors (based on JLCPCB availability) and even 0201 is relatively large compared to SOT-723.
• Where are the component values coming from? Why 100 pF and not 50 or 200? There is a lot of dependency on transistor parameters and drive waveform here. OK for a breadboard build. But I am looking for ordering a board with a few 1000 (probably poorly specified, depending on JLCPCB availability) generic transistors and obviously hand tuning the components is out of the question
• Does this allow for synchronous logic (like in an FPGA)? Means input hold time must be smaller than clock-output delay (+clock delay)? Or - would a shift register built of those work?

Thinking of it, the best way to get rid of  tco/th/clock delay issues is to use a two phase clock. I wonder if the missing transmission gate could be replaced by a back-to-back MOSFET pair? Gate drive would best be a bit above logic level, which could easily be implemented for a global clock network. Like 3.3 V logic, 5 V clock drive. See schematic.
So with some additional functions (reset, output enable) this would make around 14 transistors per bit. Together with clock drivers, LED drivers etc. a 16 bit register would amount to 250 transistors. This would make a nice module that could be plugged into a mainboard and tested/produced on its own.

BTW I was thinking of the simplest possible CPU that would make any sense. See data flow diagram. This makes a total of four registers, plus one extra for load-modify-write commands (INC $22 or so). There would be three command types:

• JMP cond.
• LDA/STA
• ALU op (add, sub, not, and, or, inc, dec, shift, cmp, test)

Adressing style for all three commands:

• immediate #33
• absolute $33
• indirect ($33)

What would be missing is JSR/RET, indexed adressing, relative jumps, stack... I guess for emulating subroutine calls some way of acessing the PC would be necessary.

Development environment: How do I test this - logic analyzer, clock generation...? As I'd install Quartus anyway (I'm an Altera guy) for ModelSim, I'd probably use some Cyclone dev board https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=167&No=921 with an interconnecting board (and optional level shifters) for emulating the memory, SignalTap as logic analyzer... which is kind of weird as such a primitive CPU would be implemented with a few lines of VHDL in the FPGA.

16 bit: Looking through the 6502, a lot of complexity is coming from having 8 bit of data, but adressing 16 bit. Like page overflow in $33,Y indexed adressing. I am tempted to make the whole thing 16 bit: 256 bytes of address space is not enough for even a simple CPU like this so to be of any use. I'd have to expand to 12...16 bits. Going to 16 bit removes the associated complexity altogether as all registers, arithmetic, PC and address bus can be 16 bit. I remember darkly that I implemented my FPGA CPU this way (>20 years ago). Of course this doubles the transistor count in the data path, but with a modular approach for the registers, this might still be feasible.

Martin

[ledtester]

A somewhat unconventional approach, but this video series details how to build a 6502 based on a Turing machine architecture...

Turing 6502 Part 1. Rule book -- Turing6502
https://youtu.be/gHU8whQP3Rg

[jmelson]

I don't like this style too much:

• 17 components! I plan to use SOT-723 transistors and 0201 resistors (based on JLCPCB availability) and even 0201 is relatively large compared to SOT-723.
• Where are the component values coming from? Why 100 pF and not 50 or 200? There is a lot of dependency on transistor parameters and drive waveform here. OK for a breadboard build. But I am looking for ordering a board with a few 1000 (probably poorly specified, depending on JLCPCB availability) generic transistors and obviously hand tuning the components is out of the question
• Does this allow for synchronous logic (like in an FPGA)? Means input hold time must be smaller than clock-output delay (+clock delay)? Or - would a shift register built of those work?

Your design below shows 13 components, so not a huge savings.  Yes, the capacitor-coupled, diode-steered FF is a true edge-triggered FF, and was used in a bunch of old computers, like DEC's PDP-5 and the LINC.
Sorry about no component values, I CAN'T find the simulation I did of this FF.  I know I did a sim to work out cap values and then built it on a breadboard.
I'm still looking for that sim so I can print out a schematic.
I really don't recommend designing a big board without making a physical prototype of at least a few representative circuits (gates, FFs, etc.) So you know what component values to use.
Jon

[Martinn]

Jon, I agree.
The reason why I tend to prefer N-MOSFET RTL is that this seems to me extremely robust in terms of parameter sensitivity. If Vgsth, Qg and maybe Rdson has the right order of magnitude, it will work. Maybe it is slow, but then you reduce the clock speed appropriately.
For bipolar capacitor coupled logic, you probably need to characterise your components (the transistors in particular) very accurately for it to work reliably. I don't see this as realistic for "noname" chinese JLCPCB components.

Martin

[tim_]

Nice project!

Jon, I agree.
The reason why I tend to prefer N-MOSFET RTL is that this seems to me extremely robust in terms of parameter sensitivity. If Vgsth, Qg and maybe Rdson has the right order of magnitude, it will work. Maybe it is slow, but then you reduce the clock speed appropriately.
For bipolar capacitor coupled logic, you probably need to characterise your components (the transistors in particular) very accurately for it to work reliably. I don't see this as realistic for "noname" chinese JLCPCB components.

RTL is actually quite robust if your take care of proper dimensioning of the resistors according to fan out. Otherwise the CDC6600 probably would not have worked with 400000 1960ies quality transistors The only issue I found is that the storage time of no-name transitors varied quite a bit from the datasheet.

I had comparatively more trouble with off-brand 2N7002 as sometimes the RDSON was not even close to the spice models. But, of course nmos is nice because you can build more gate types from it.

[tim_]

For the layout/sim workflow I highly recommend checking out this guys project
https://hackaday.io/project/180839/logs

It's really interesting and also made me seriously consider doing a discrete CPU, probably writing some of the place and route and layout tools myself.

Thanks for mentioning this!

You can also find the current version here:

https://github.com/cpldcpu/PCBFlow

I should probably add a walk through so others can use it as well.

[tim_]

Thinking of it, the best way to get rid of  tco/th/clock delay issues is to use a two phase clock. I wonder if the missing transmission gate could be replaced by a back-to-back MOSFET pair? Gate drive would best be a bit above logic level, which could easily be implemented for a global clock network. Like 3.3 V logic, 5 V clock drive. See schematic.
So with some additional functions (reset, output enable) this would make around 14 transistors per bit. Together with clock drivers, LED drivers etc. a 16 bit register would amount to 250 transistors. This would make a nice module that could be plugged into a mainboard and tested/produced on its own.

Btw, just a short though experiment. Consider the output of your latch is high (Q=1), how can it be switched to low?

[Martinn]

Btw, just a short though experiment. Consider the output of your latch is high (Q=1), how can it be switched to low?

Nice... found a bug already! One should really run simulations before posting schematics.

[Martinn]

Some progress...

PCB arrived from JLC. I decided to try two phase latches (four implemented) with an incrementer to the right.
For testing and clock generation, I'll plug it into a Cyclone V FPGA development board.
On this PCB, I also tested the idea of "super" gates: https://pastraiser.com/technology/nmos/basicnmosgates.html
which seem to be a workaround from the nmos only era to get around the slow rise time caused by the pullup element, without having a pmos transistor. I used those for the clock drivers, as they'll see more load and are more time critical.
I thought this might be a solution for reducing shoot-through (cross conduction) in a complementary pair, but simulation showed it is even worse. I used it nonetheless (with some series resistor in the top path) as I was unable to find a decent (low Vgsth, low Qg) p channel MOSFET in the JLC catalog.
BTW Honza has improved the MOSFET search function https://yaqwsx.github.io/jlcparts/#/ in his fantastic JLC catalog - thanks a lot!

[Martinn]

While I am waiting for the development board to arrive, I implemented Tims workflow https://hackaday.io/project/180839-vhdlverilog-to-discrete-logic-flow
KiCad files are easily modified to add both components and place them in the layout, see https://forum.kicad.info/t/programmatically-generating-schematic/32518
I think I have the ALU now more or less fixed, not sure about the interfaces yet.
Mainly for fun I synthesized a 8x8->16 bit multiplier - purely combinatorial "single cycle" (not stating how long that cycle would be).
KiCad had no problem with this, Freerouting completed the board in about 3 hours. Not bad.

Right now I am working on a VHDL implementation of the CPU which I could run in Modelsim, on the FPGA and then I can component for component replace the FPGA implementation with the discrete board, until ideally only clock generator and RAM stays in the FPGA.

[SiliconWizard]

The HP-35 calculator has a serial (1 bit) CPU - maybe build something like this? However, debugging is nasty as you always have to decode a serial bitstream.

If you want to minimize logic while having some challenge, going for a "serial" CPU sounds interesting. And, with this approach, there's a whole lot of things that become doable (like implementing an hardware multiplier and divider), while doing it with wider words would become unpractical, or would require going serial anyway, and then back.

I personally wouldn't design a discrete CPU these days - I've done this on FPGAs for a while - but if I was going to, for the challenge or fun or for educating others, I would definitely go the serial route!

For debugging, all you need is a logic analyzer - which would come in handy for debugging any kind of CPU anyway IMO. (I have a DSLogic Plus that I happen to like, but there are many options out there.)

[Martinn]

A serial CPU would indeed be a challenge.
What I imagine being the most difficult for both simulation and debugging is that you somehow have to decode/visualize the entire bitstream (56 bits in case of the HP-35) to find out if it does what it should.
With standard parallel design it is much easier to see what is going on - see screenshot (my VHDL CPU doing its first steps... JMP absolute back and forth)