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Divide by 10000000
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jpb:

--- Quote from: Fungus on May 31, 2017, 09:53:35 am ---If you want it to be 'cool' you can use decade counters:

eg. 74LS163

http://users.ece.utexas.edu/~valvano/Datasheets/74LS163.pdf

Each one will divide by ten, just join a few together.

(...and if you want to be 'retro' you can do it all with 74LS flip-flops. The details are left as an exercise for the reader.  :popcorn: )

--- End quote ---

This is the approach that James Miller does (to get down 10 10kHz so not quite as far) in his simple but good GPSDO:

http://www.jrmiller.demon.co.uk/projects/ministd/frqstd.htm

Each chip can divide by 100 so 4 of them would be required, rather a lot of board space but simple and cheap.
james_s:
I'd use a small CPLD like the XC9536, I'm already set up to work with those though.
edavid:

--- Quote from: Dr. Frank on May 31, 2017, 05:38:26 pm ---Using ordinary TTL divider-by-10 is no good idea, because these are mostly asynchronous dividers, having big jitter.

--- End quote ---
You can fix this by clocking the output through a good flip flop (as long as the jitter is less than 1 clock cycle).
(Or for a synchronous divider, 74HC4518 is a good choice.)


--- Quote ---The  delay time is strongly temperature dependent, also on synchronous dividers, afaik, so not good at all for T.I. measurements.

--- End quote ---
Why would a logic part be worse than a PIC?  CMOS is CMOS.
Marco:

--- Quote from: blueskull on May 31, 2017, 08:54:57 am ---I don't know how it's measured, but according to some FPGAs' datasheets, even hard PLLs can't guarantee to generate such clean clock.

--- End quote ---

A PLL uses it's own inferior oscillator. A pure synchronous divider will always have the advantage in that respect, even if it's a PIC.
Dr. Frank:

--- Quote from: edavid on May 31, 2017, 06:22:50 pm ---
--- Quote from: Dr. Frank on May 31, 2017, 05:38:26 pm ---Using ordinary TTL divider-by-10 is no good idea, because these are mostly asynchronous dividers, having big jitter.
The  delay time is strongly temperature dependent, also on synchronous dividers, afaik, so not good at all for T.I. measurements.

--- End quote ---
Why would a logic part be worse than a PIC?  CMOS is CMOS.

--- End quote ---

There was a lengthy discussion on the time-nuts list, but I don't catch the correct argument anymore, too long ago, sorry.
A synchronous divider chain is for sure much less effort, than carefully programming the PIC, so there's a good reasoning, why the PIC solution is much superior.

A 10^7 divider chain consists of 28 flip flops, each having about 25ns delay.
Even if it's synchronized, that gives rise to delay jitter, which a state machine does not have, because it's no FF chain inside.. and that's the difference.

Maybe it's possible to search  time-nuts for that topic.

Frank
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