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Divide by 10000000
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Marco:

--- Quote from: Dr. Frank on May 31, 2017, 07:37:42 pm ---Even if it's synchronized, that gives rise to delay jitter, which a state machine does not have, because it's no FF chain inside.. and that's the difference.

--- End quote ---

AFAICS standard logic counter doesn't ripple the result through all the flipflops every cycle, it is a state machine which uses the internal state from the previous cycle with logic gates to determine what to output on the next clock. Each flipflop is just an individual clocked latch.
edavid:

--- Quote from: Dr. Frank on May 31, 2017, 07:37:42 pm ---A 10^7 divider chain consists of 28 flip flops, each having about 25ns delay.

--- End quote ---
I don't see how that is relevant.  The delays do not cascade, except in the case of a ripple counter.


--- Quote ---Even if it's synchronized, that gives rise to delay jitter, which a state machine does not have, because it's no FF chain inside.. and that's the difference.

--- End quote ---
I don't see that.  Surely for all 3 cases (ripple counter + synchronizer, synchronous counter, MCU state machine), the output delay jitter is only due to the final stage.
 
edavid:

--- Quote from: mikerj on May 31, 2017, 08:29:22 am ---If you are clocking the micro from the GPS 10MHz clock, and the division is performed by a timer rather then software, then you are only adding the residual jitter from the hardware timer.  This isn't something you'd ever see specified in a datasheet,  do you have any numbers?

--- End quote ---

The whole point of PICDIV is that if you clock the micro from the 10MHz input, you don't need a hardware timer, because software timing is about as good.
jpb:

--- Quote from: Dr. Frank on May 31, 2017, 07:37:42 pm ---
--- Quote from: edavid on May 31, 2017, 06:22:50 pm ---
--- Quote from: Dr. Frank on May 31, 2017, 05:38:26 pm ---Using ordinary TTL divider-by-10 is no good idea, because these are mostly asynchronous dividers, having big jitter.
The  delay time is strongly temperature dependent, also on synchronous dividers, afaik, so not good at all for T.I. measurements.

--- End quote ---
Why would a logic part be worse than a PIC?  CMOS is CMOS.

--- End quote ---

There was a lengthy discussion on the time-nuts list, but I don't catch the correct argument anymore, too long ago, sorry.
A synchronous divider chain is for sure much less effort, than carefully programming the PIC, so there's a good reasoning, why the PIC solution is much superior.

A 10^7 divider chain consists of 28 flip flops, each having about 25ns delay.
Even if it's synchronized, that gives rise to delay jitter, which a state machine does not have, because it's no FF chain inside.. and that's the difference.

Maybe it's possible to search  time-nuts for that topic.

Frank

--- End quote ---
You could use a synchronous counter and then a final latch (flip flop) that was armed but then switched from the original signal but then the circuit is getting more complicated.
BrianHG:
ARRRGGG, this is kinda getting nuts.  If you want your PIC output 1 second high/low pulse to sit right on a rising edge of the 10 MHZ source any better than it already does, just put the PIC output to the data in of a 74AC74 D-latch flipflop and tie the flip-flop's clock input to the 10MHz source clock.

Running a cheap loop in the pic to count the equivalent of 5 million clock ins, output high, another 5 million clocks in and output low, without any PLL or timer is a brainless trivial piece of loop code in assembly.  No PLL, no timer, no watchdog, no interrupts, no special sleep cycles, nothing else needed, it will just run without fail.  Making the code pulse the output pin high/low as quick as it can after every 10 million clocks is the same 10-15 lines of assembly code.


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