Now I understand that you want to compensate for the offset resulting from the polarization currents. Resistor methods were used for bipolar amplifiers where the current Ib was the base current, making it large (nA) and repeatable, while the current Ios was small and resulted from the asymmetry of the input stage. In FET amplifiers, the Ib current doesn't flow into the gate; instead, it's the difference in current from the ESD protection diodes. Therefore, it can vary significantly for both inputs, even flowing in opposite directions. Ios>Ib is not surprising. Diode leakage currents increase exponentially with temperature, so they can be many nanoamps at 125°C. This is why the maximum from the datasheet can be so high. However, the probe will not be used above room temperature.
Your compensation method should be tested in practice. A simulation won't tell you if it works.
I needed a fast probe, so I was only considering amplifiers >50MHz. These amplifiers have an offset >200uV. Above 70MHz, it's difficult to find an offset smaller than 2mV. That's why I wasn't expecting microvolt accuracy. It is known that a capacitive probe does not transmit DC, so if anything appears at the output, we can consider it to be an amplifier offset or a leakage current from the input capacitor. We can even block the DC component at the buffer output.
In fact, the impedance of C2 is so high that the HINIB of the active adaptor requires a resistor from the noninverting input to ground in order to not fry, which is now our R2.
Without R2, the circuit will saturate and won't work.
Due to the polarization current, a resistor R2 is necessary, the disadvantage of which is that it limits the bandwidth from below. That's why I'm considering bootstrapping to increase the effective value of this resistor.
R2 will have to be used in the compensation equation: R1xC1=R2xC2, but it can be anything you want, although I'm not sure what it should be in relation to C2's DF or if it matters.
The capacitive divider will not be compensated (R1 non existent), but that doesn't matter because the bandwidth limitation will be <200Hz. In theory, a capacitive divider has no upper bandwidth limit, but it is known that the stray inductance of real capacitors will prevent "microwave" operation
DC can be transferred using a separate low frequency resistive probe if needed. DF of PTFE should be low.
The reason why I ask about a virtual ground is because of the active adaptor's input offset and the possiblity of limiting the common mode capacitance thats grounded, due to the BNC cable on the non inverting input.
I didn't plan for the cable to be before the buffer because if the cable is after the buffer, it can be matched to 50R.
I don't know what the parameters of the capacitive divider directly connected to the cable will be. The RG-58 50R cable has about 100pF/m, but I'm worried about reflections. I'd have to try. Maybe it's better to cannibalize the cheap probe and get a lossy cable from it.
I came up with the idea that I could suppress reflections with a resistor inserted between the capacitive divider and the cable, an example from the simulation is shown below. The total capacitance of C2 is 200pF, of which 100pF is the cable. It even works somehow, but I don't expect this simulation to accurately represent reality. Beside, a 30ns ringing decay time is not a good result, my primitive probe without an amplifier and cable was better.
I don't see a capacitive divider or cable in your diagram, so the details are unclear to me.
I'm not sure if using a virtual ground though will limit the C(cm).
I don't quite understand. I was only considering single-ended probe. I don't see anything that justifies introducing a common-mode/differential-mode distinction. Do you mean the amplifier's internal capacitance?
The key point is that if all 4 op amps have about the same offset, you can use their own offset to null the total offset.
Amplifiers in a single package do not have identical offsets. And there's no reason they should. Beside, we don't know if the observed offset is a real asymmetry in the input transistors or the remaining inaccuracy after the manufacturer performed offset trimming.