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DIY oscilloscope (yet again)
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gf:

--- Quote from: David Hess on November 23, 2019, 06:11:23 pm ---No, I mean many low cost USB and "toy" DSOs use a 12 bit ADC but only return 8 bit results except in high resolution mode. The extra 4 bits are only used in place of a PGA.

--- End quote ---

OK. At lower speeds, 12-bit ADC is certainly not so challenging as at 1GSPS.


--- Quote ---What the HMCAD1511 does relies on the error correction included in its pipelined subranging ADC design which is different as it is not designed to return 12 bit results.

--- End quote ---

It works differently, but eventuelly it can act as a PGA as well, up to gain of 50 (when both, coarse and fine gain are turned up to the maximum). The application notes recommend, however, not to choose a gain > 10, otherwise SNR suffers.

While it returns 8 bits only, the returned value is already scaled by the selected "digital gain", having ENOB of still almost 8 bits (in the recommended gain range).


--- Quote from: Application Notes ---"This feature is based on the fact that the HMCAD1511, though it is an 8-bit converter, has more resolution available in its core circuitry. This means that although the SNR available to the user is limited by the quantization noise floor of an 8-bit converter, the actual noise floor deep within the ADC’s core is significantly lower than that."
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David Hess:

--- Quote from: gf on November 24, 2019, 12:01:02 am ---
--- Quote from: David Hess on November 23, 2019, 06:11:23 pm ---No, I mean many low cost USB and "toy" DSOs use a 12 bit ADC but only return 8 bit results except in high resolution mode. The extra 4 bits are only used in place of a PGA.
--- End quote ---

OK. At lower speeds, 12-bit ADC is certainly not so challenging as at 1GSPS.
--- End quote ---

Lower is relative.  12 bit settling, noise, and linearity are very challenging at even low oscilloscope bandwidths.

I have seen very old 100 MHz 8 bit DSOs which delivered better than 8 bit noise (1) but I have never seen a modern 8 bit instrument achieve the same thing.  Part of it is the result of software upgradable bandwidth which means the hardware is designed for a higher than necessary bandwidth resulting in higher device noise.  Another part is the use of CMOS preamplifiers that have much higher noise than the bipolar preamplifiers they replaced.  The physics of today is the same as the physics of 30 years ago.

Oscilloscope noise is rarely a concern however so higher noise than 30 years ago is not really a disadvantage.  If you need a lower noise oscilloscope, then there is probably a better way to make your measurement.  But I still chuckle that seemingly every marketing department advertises their oscilloscopes as "low noise" now.

(1) It is a little weird to turn the vertical position control and be able to select a single ADC code with little or no noise producing a straight line.  A noisier signal looks more natural.
gf:

--- Quote from: David Hess on November 24, 2019, 02:34:16 am ---I have seen very old 100 MHz 8 bit DSOs which delivered better than 8 bit noise (1) but I have never seen a modern 8 bit instrument achieve the same thing.

--- End quote ---

At 10V/div, 1V/div and 100mV/div, the analog SNR seems indeed too exceed 8 bits on my Hantek 6074BD (only sporadic 1 LSB spikes). These are the attenuator steps where the HMCAD1511 gets driven at 2Vpp full-scale, w/o unnecessary attenuation and subsequent re-amplification in the signal chain. All other V/div steps rely on re-amplification (via digital gain) of the 10:1 or 100:1 pre-attenuated input signal and are noticeably noisier.

[ Yet another candidate for unnecessary attenuation and subsequent re-amplification I'm aware of is the Hantek 2000. Every V/div step is first attenuated to a 10mV/div equivalent and then (re-)amplified to the ADC's required full-scale voltage by a (fixed) gain stage. ]


--- Quote ---Part of it is the result of software upgradable bandwidth which means the hardware is designed for a higher than necessary bandwidth resulting in higher device noise.

--- End quote ---

(Unnecessary) bandwidth is certainly a significant contributor. On my JyeTech DSO 112a toy scope (~50 bucks, ~1-2MHz bandwidth), I can clearly see ~1.2mV quantization steps in the output of a DDS generator. But on my 1GSPS Hantek 6074BD, these steps drown in noise...
PMA:
Here is my war plan for the first test. I will make 1ch on separate PCB and attach it to PYNQ-board with ribbon cable (not sure if this is good idea for high speed data).

Edit:
PLL chip for ADC: ADF4360-7
Relays: NEC UD2

I have seen two variants of ADC buffer. In some designs ADC is driven with PGA without any additional components and in some designs there is additional buffer between them. I don't fully understand why additional buffer is needed because output impedance of the PGAs are typically quite low. What are pros and cons of these design choices?
Yansi:
good find on that AD8370!
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