DIY oscilloscope front end queries

[WattsUp]

Hello,

  I have recently undertaken a rather large project, to create an oscilloscope, complete with TFT display, physical controls and a somewhat usable bandwidth limit. I have looked at various examples online, but none (except one from which I learnt much information from, but was not quite advanced enough for me) were more than an Arduino reading an analogue input. My motivation for this is to learn more about how scopes work, analogue circuitry and uCs in general. The bandwidth aspect will be determined as time goes on.

  My query relates to the front end design, more specifically the use of attenuators and amplifiers. I am aware of what they do (reduce and increase a signal's strength), but I am unsure of their use in an oscilloscope, especially since many of the block diagrams I have viewed vary in this respect; some have either, neither or both. Could anyone tell me more about their application specific uses please, and where they would fit into my 'schematic' as attached below.

  Advice on the feasibility and overall design of this scope is also welcome, either through the thread or PM. Also, I would appreciate it if someone could just look over my existing schematic and tell me if it has any chance of working, as well as where the attenuator/amplifier would fit in. Before ADC, for example?
Regards,
Ben

EDIT: AC is the analogue comparator which will be used to set the trigger threshold

[c4757p]

Just poking my head in briefly for now, but I'll point you to this, and more importantly here where I've actually got some frontend stuff.

I've got my frontend mostly designed now, and I've gone into quite a bit of detail on the purpose of every part in the front-front section (right after the input jacks). I should put up some Bode plots and whatnot, I suppose. buh, documentation

[c4757p]

More importantly, have you selected an ADC? I'd highly recommend choosing one early. You know the signal amplitude you need to have at the ADC, and you have the signal amplitude ranges that you expect at the inputs - now work inward from both points. Depending on your bandwidth, it'll be tricky to get the right amounts of gain and attenuation in the right places to make sure everything has a signal at a comfortable level regardless of the selected range.

[w2aew]

The classic (simplified) approach is to design a fixed gain front end amplifier that has sufficient gain for the lowest signal level you plan to accommodate, and then put an adjustable passive attenuator in front of it. By taking 'adjustable gain' off of the table for the preamp, you can concentrate your efforts on transient response, bandwidth, flatness, overload recovery, linearity, etc.

[T3sl4co1l]

More importantly, have you selected an ADC? I'd highly recommend choosing one early. You know the signal amplitude you need to have at the ADC, and you have the signal amplitude ranges that you expect at the inputs - now work inward from both points. Depending on your bandwidth, it'll be tricky to get the right amounts of gain and attenuation in the right places to make sure everything has a signal at a comfortable level regardless of the selected range.

Yup.  Note that ADCs have two basic frequency characteristics: the sampling rate, and the analog bandwidth (usually dominated by the input switch resistance working into the sampling capacitance).  Many ADCs have both parameters nearby (e.g., your average Arduino internal ADC has an equivalent circuit something like 10kohm + 10pF, or a cutoff of 1.6MHz, with a maximum sample rate of, at best, fractional MHz), but some have considerably greater analog bandwidth.  High sample rate ADCs are a good example, as they are frequently intended for SDR type applications: a sample rate of 65 or 80MHz, with analog bandwidth of 1000MHz or more.

What's the point?  It allows you to sample a signal with much higher frequency content than your sample rate, so you can do frequency conversion (for an SDR, no need for an input converter stage) and equivalent time sampling.  You still need timing accuracy comparable to the signal, so your trigger detector circuit needs to be very fast, low jitter, and routed straight to the ADC (not something you can control in software -- for example, any timing generated internally on an Arduino, whether by software or built-in timers, is intrinsically driven by the clock rate, 20MHz at the most).

If, for whatever reason, you can't get an ADC with the desired analog bandwidth, you can employ a sample-and-hold circuit with a faster "aperture" time, to momentarily store the signal before converting it.  This is the basis of all high speed sampling oscilloscopes, since their invention.  (Your average entry-level DSO these days is direct conversion, of course, but the bleeding fast ones break up the signal and feed multiple converters.)

Tim

[tggzzz]

Have a look at http://www.ti.com/lit/ds/symlink/lmh6518.pdf

[nuno]

I would really like to see an Open Source "normal form factor" oscilloscope. Me and some friends, we sometimes toy with the idea in our minds. Most of it is just design and learning exercise. The target specs would be low since we're not experts in this field at all, and the scope would be built to be low cost. But being OS the back end software could reach an interesting state of development. So we imagined we could do a scope 25MHz 200msps 1chn / 100msps 2chn 4KB total mem. We have some ideas for the architecture; analog attenuator with 2 or 3 positions, jfet input buffer, x10 gain buffer, ADC, a "discreet" logic acquisition block (no FPGA) and RaspPi+TFT/LCD module for high level control/UI/post processing.

I gather some information about this topic here:
https://docs.google.com/document/d/1xqnG20M7uSh7b6l7MWh_v6OnK6OmlYJReyGQzc51Q54/edit?usp=sharing

I have searched a little and I'm leanning towards specific ICs for some functions:

-- Clock Generator: 501MLFT  IDT (PLL Clock Multiplier)
In: crystal, 2 - 27MHz
Out: upto 160MHz

-- ADC: Analog Devices AD9283BRSZ-100
There are versions from 50Msps, which is nice to allow starting "slow" and keep the development costs low.

[WattsUp]

  Thank you all for your replies.

  c4757p, your design has given me much more information, and I appreciate that you are sharing your schematic for others to build upon. I have sent you a PM with a few questions related to your design. W2aew, does doing this mean that instead of adjusting the amplification of a signal, you just adjust the attenuation. Does this improve the signal fidelity (among other benefits), or is it just an easier way to 'prepare' the signal to feed into the ADC? In regard to the statements surrounding the ADC, I am unsure of the part to pick, simply because of the sheer number of options. They are also expensive, and I can't really afford to buy a range of parts. If anyone has any suggestions, please share them; I was thinking of dual ADCs, each 500 Ms/s, so 250 Ms/s per channel for all of the four channels which I hope to implement, but looking at the cost for an 8 bit 500 Ms/s ADC, I think that figure might have to drop.

 nuno, this was what I was looking for when I first conceived of this project, but I found the results of a quick google were nothing but crappy kits, basically useless Arduino versions and unfinished, yet promising, scopes. My target goals, seeing the work done by c4757p as well as a few others, have increased, to a minimum (?) of 50MHz, 100 Ms/s + per each of the 4 channels, and a colour TFT display. I currently have no clue as to other DSO specific factors such as sample memory. My reason for this being that I want it to be useful, a tool that can be used in conjunction with my 20MHz analogue scope. One (more) thing I'm unsure about is how the maximum bandwidth is decided. Is the main factor the ADC, so long as the rest of the circuitry works at that frequency; I think it was on one of Alan's videos that I saw bandwidth is measured at -3dB.

Thanks again for your continued support,
Ben

[c4757p]

In the future, if you have questions about my design could you ask them in the thread? The answers could be useful to more people.

[nctnico]

How far does DIY go? Once you are done you'll be looking at a component cost which is considerably higher than buying a readily made oscilloscope.

IMHO it would be more interesting to buy a cheap oscilloscope (Owon or Hantek for example) and write your own firmware for it.

[c4757p]

IMHO it would be more interesting to buy a cheap oscilloscope (Owon or Hantek for example) and write your own firmware for it.

Depends, I guess, on whether you'd rather do hardware or software!

You're right though, it won't be cheap.

[WattsUp]

  Sorry, I just thought I would ask you directly since it is your design, I will address questions via the thread from now on. nctnico, I can not afford the upfront cost of even that low end scope, and I have no experience writing firmware anyway. I'm in it more for the learning experience than to get the finished product, and I'm in no rush. I'd also like to see how cheap I can go for some level of usability.
Ben

[nuno]

nuno, this was what I was looking for when I first conceived of this project, but I found the results of a quick google were nothing but crappy kits, basically useless Arduino versions and unfinished, yet promising, scopes.

Yeah, I don't know of any decent 20MHz or so normal form factor scope. There are Gsps open stuff out there, but as computer modules, and quite expensive. I think 25MHz or so is pretty decent, specially when there's the possibility of having "lots" of people work on software and vastly improving the tool's utility.

My target goals, seeing the work done by c4757p as well as a few others, have increased, to a minimum (?) of 50MHz, 100 Ms/s + per each of the 4 channels, and a colour TFT display. I currently have no clue as to other DSO specific factors such as sample memory. My reason for this being that I want it to be useful, a tool that can be used in conjunction with my 20MHz analogue scope. One (more) thing I'm unsure about is how the maximum bandwidth is decided. Is the main factor the ADC, so long as the rest of the circuitry works at that frequency; I think it was on one of Alan's videos that I saw bandwidth is measured at -3dB.

I don't dare to shoot that high to start. My goal would be to be able to use the 1chn 200Msps to measure signal raise times of 50ns 5ns (1/200MHz), "squeezing" out as much as possible out of the sampling rate, but that implies an analog bandwidth of some 70MHz (using the 0.35 constant...); I'll have to see what I'm able to do. For several reasons I don't want to have signals (analog or digital) running at more than 100MHz, and I've seen it's not "impossible" to do discreet front-ends up to 100MHz or so. This is totally exploratory for me, and since I don't have a background on this stuff, I'm willing to try some less conventional approaches while aiming at simplicity and low cost.

There are 2 or 3 links to very good stuff on scope front-ends in the google doc I left above, you should check it out too. As I see it, in general is more expensive and complex to have a programmable gain amplifier.

For me it is not a matter of price or need (I already own 2 Rigols and a 20MHz older analog), it's one of not having "to eat" stupid bugs on something that still costs money, and of being able to improve it.

I'm looking forward to exchange ideas and whatever else.

[nctnico]

Over a decade ago I embarked on a similar adventure and actually got close to a completed product. The hardware is the easiest part of the project. The software (including VHDL) however is a different story. I estimate the time needed for software versus hardware is about 50 to 1. If you can somehow participate in a project which aims to develop oscilloscope firmware you'll be getting to an end result quicker.

My initial design was around a 100Ms/s 10 bit ADC but I was in the process of going to 250Ms/s and 12 bit. I designed the frontend in the attached PDF file based on the front-ends I built before (this is the 4th generation). It uses a set of varicaps (driven by a digitally controlled 0..50V tuning voltage) to compensate the input divider by the software making adjustment during production easier. Furthermore it has a 100MHz elliptic filter; this may be too steep though. In the software I used a 20th (or something) polynomal approximation to allow frequencies up to 0.45fs. What isn't on the schematic is an ultra low jitter clock source. For 12 bit at 250Ms/s you'd need an oscillalator with sub ps jitter. I never got to testing my new front-end though because I canned the project.

[WattsUp]

I completely missed those great resources, so thanks for sharing. TBH, not having much experience here either, I just ran with the first thing I found; I should have spent more time researching before jumping to designing something. I understand what you are saying with the channels, since they add cost and some complexity, but the opportunity is there to expand the design with a little effort to more channels, if you design a decent front end. In regard to the bandwidth, I'm sure you are more qualified to set an attainable goal than I (I was aiming for most useful over the actual possibility to design and make it!). When it comes to software, though, I'm at a loss. Since the point of this scope was to learn, the programming side would just have to try and keep up!

  I'll try and research some more methods, and report back here if I find anything useful.
Regards,
Ben

[WattsUp]

 I've managed to find a few resources, the best being this. Looking at that front-end schematic has reassured me that the direction I am heading is attainable.
Ben

[T3sl4co1l]

I've managed to find a few resources, the best being this. Looking at that front-end schematic has reassured me that the direction I am heading is attainable.
Ben

Direct link; https://dl.dropboxusercontent.com/u/37077406/Website%20Links/6.111%20Final%20Analog%20Front%20End%20Schematic.pdf

  The "AC/DC" switch is a capacitor into the (high-Z) input pin or not!

And by I mean I loudly conducted the physical gesture the second I spotted it...

Also, the "antialiasing filter" is a 25MHz single pole RC filter.  Out of 100MSa/s (200 possible).  That's barely going to do the job if it were a 5-pole Bessel!

I would much rather simply not attempt to AA filter it in the first place, and tweak as good a high frequency (step) response as I can (which will be limited by the op-amps and ADC).  Especially with a paltry 100MSa/s, which doesn't pass for real time scopes these days, but would be perfectly acceptable with some trigger and ET hardware.

Tim

[Liv]

That is much more adequate front-end.

[Marco]

Dave drew a Rigol front end in Davecad in one of his episode, they used a two path source follower ... but I don't really know why you would do that for these relatively low frequencies. You can get a lower input capacitance with a bootstrapped source follower than some integrated buffer, but you don't need it. So save yourself the headache.

Take a look at the Owon and the DSLogic frontends (note that with the DSLogic frontend you're not supposed to do a straight pass through of the signal with the relay, it's always at least attenuated 2x).

PS. I don't really see the point in anti-aliasing in an oscilloscope ... in one way or another the high frequency components are going to  screw things up regardless, whether they alias or not. Low pass is only needed for noise reduction.

[T3sl4co1l]

That is much more adequate front-end.

Mmm, looks pretty good, I wouldn't push such a divider ratio for the internal step (1/50 to 1 on sequence), I'd rather see that done on a decade basis I think (1-2-5, then two 10x), but it's probably not as bad as I imagine.  But then 4051: there's no way you're getting much bandwidth through that!  A DG400 series switch, or something like that, would be much better.  Also didn't check if any of the op-amps are consistent in terms of gain-bandwidth, or what the ADC runs at.  If it's all on the slow side (<10MHz?), this is all fine.

Tim

[Liv]

I wouldn't push such a divider ratio for the internal step (1/50 to 1 on sequence), I'd rather see that done on a decade basis I think (1-2-5, then two 10x)

1-2-5-10-20-50 is equivalent to two stages(1-2-5 and 10x), but realized at one stage. Scheme can be improved somewhat by adding resistors, matching output impedance divider for each output. Then the bandwidth will not change. And worst of all for the oscilloscope when changing bandwidth when changing V/div. For example, you can not try to change the gain of the stage at the opamp, as this will cause a change in bandwidth. Scheme with a passive divider is free from this drawback.

But then 4051: there's no way you're getting much bandwidth through that!

74HC4051 (not CD4051B!) not so bad (see attached plot). This graph is made to 50 ohms, but the impedance of the divider is also relatively low, which makes a fast circuit.

You can apply and faster switch. For example, the GDS-810 uses the AD8184 video multiplexer in such a scheme.

If it's all on the slow side (<10MHz?), this is all fine.

This open has a sampling frequency of 100 MHz and a bandwidth of 20 MHz.

[LaserSteve]

If one just wants to play with stock parts:

http://www.knjn.com/Flashy.html 

I have a design article written by a TEK Engineer at  home on how to do a 1 Ghz front end with split DC and AC paths.
I'll scan it in tonight and post a link.

Steve

[Liv]

"Signal Conditioning in Oscilloscopes" by Steve Roach.

But most of the information relates to the very fast schemes and unusable for DIY projects.

[JoeN]

I hope nobody minds if I resuscitate this topic.  I have something to add here.

After this thread occurred, TI published a reference design for a 2 Ghz scope front end last year.  I am going to link it here.

What do you think of their design?  All high-spec parts, for sure.  The one thing that adds a bunch of cost to this is the RF relays they are using for their attenuator are $50 each and they use 5 of them.   Most of the TI parts, despite really high end performance, are downright cheap compared to those relays (not inclusive of the ADC!).  I assume there is no way to achieve that using some sort of RF IC switches?

Page: http://www.ti.com/tool/TIDA-00826
Schematic: http://www.ti.com/lit/df/tidrjw1/tidrjw1.pdf   
User guide: http://www.ti.com/lit/ug/tiduba4/tiduba4.pdf

[BravoV]

Hmmm ... schematic checked, documentation checked, gerber files checked, then clicked the buy button on the ADC, and TI is telling me to pay $3,611.18  ... instantaneously emptied the "My cart" , and closed the tab at the browser.