Please put actual information about your question in the topic.
Last I checked there were no "TCP stack on a chip" implementations that operated at 1G. So you will need a standard ethernet PHY connected over either (R)GMII or SGMII.
Implementing a simple datagram packet handler on an FPGA is fairly simple, although be prepared to spend a lot of time reading documentation. TCP connectivity is much more complex and a much better fit for a microprocessor. That could be a microblaze processor, but I don't know what the performance will be like since you are making gigabit a requirement. Sustaining gigabit throughput TCP on links of moderate latency also requires a lot of RAM, so you will probably need DRAM as well the onboard SRAM will not be enough. For instance, 1 gigabit/s at 20 ms round trip time is a bandwidth-delay product of 2.5 megabytes. Your TCP sender needs at least that much buffer memory to avoid stalling, more to account for high latency bursts or packet loss.
Honestly I don't think this is a good project for someone who is saying you have limited money _and_ time. The fastest approach would be to use an off the shelf dev board with an SoC FPGA and just let the ARM processor talk networking, but AFAIK the intersection of "cheap" FPGA dev boards and those with _dual_ ethernet is null.