Real world transistor biasing: What's a typical process?

[TimNJ]

Hi everyone,

As a fourth year EE student, I've solved many problems with transistors, doing bias calculations, small signal modeling etc. These exercises are all good and well but I still feel like there is a disconnect between what we learn from our textbook (in this case Sedra/Smith) and how "real engineers" design transistor circuits the real world. By this I mean: Many times we are given constants that wouldn't be provided in a real datasheet (k, a trans-conductance parameter, for example) OR we are given a set of assumptions that seemingly come out of thin air (like assume the drain current is X).

I've hunted around many forums and many many documents trying to figure out what a good practical approach is to designing transistor circuits with values available in the datasheet and with a given set of constraints. Most of the literature I've seen is academic in nature, and while true, seems a bit impractical(??) In fact, I've seen many forum posts that say "Here is how you would solve this, but we would never do it this way in the real world"...and then do not explain how they would do it.

I know this is a very open ended question, so maybe I should narrow it down. In the case of a common source FET amplifier or common emitter BJT amplifier, what would be your general steps to properly establishing a bias point?

Thanks. I really appreciate it.

[Benta]

In practice, you'll always be faced with two things:
input source (voltage, current, impedance, frequency range)
Output load (the same)

The output load will define your DC collector current - it'll have to be as large as the load needs.
From there, work backwards. Select the DC operating point (emitter resistor and base voltage), define the HFE you need (using minimum value from the datasheet) and design your base voltage divider from that.

I've left out emitter capacitors for AC gain enhancement on purpose.

Nobody uses this anymore, it's a relict from the times when transistors were expensive. Today, you can design amplifiers that are purely DC, simply because the devices are so cheap.

[TimNJ]

In practice, you'll always be faced with two things:
input source (voltage, current, impedance, frequency range)
Output load (the same)

The output load will define your DC collector current - it'll have to be as large as the load needs.
From there, work backwards. Select the DC operating point (emitter resistor and base voltage), define the HFE you need (using minimum value from the datasheet) and design your base voltage divider from that.

Thank you. I've been having a really hard time selecting a proper DC drain/collector current for a given load. Everything makes sense in the non loaded case. The equation relating drain current to Vgs tells us that for a given overdrive voltage (Vgs-Vt), the conducting channel must conduct some current. When you change Vgs, you change the current that must flow. That current has to come from somewhere so, in the common source case, it is pull through the drain resistor RD which causes a greater drop across that resistor, swinging the voltage at the drain.

That's fine. But now if you attach a given load (through a coupling cap), whenever the input changes (above a certain frequency), the transistor now "sees" a load attached to its drain. As the voltage at the drain changes, current is either driven into or pulled from the load. To me, it seems like there are some simultaneous equations going on(?). For a given quiescent drain current, how can you quantify the voltage swing at a given load? Do people usually calculate that as part of their design? Rules of thumb? Make RL >> RD?

I've left out emitter capacitors for AC gain enhancement on purpose.

Nobody uses this anymore, it's a relict from the times when transistors were expensive. Today, you can design amplifiers that are purely DC, simply because the devices are so cheap

Really? Why would we not be interested in gain enhancement? My understanding is that high frequency AC signals bypass the emitter resistor and thus gain is improved.

I know op-amps are basically perfect DC amplifiers. Is that what you're referring to?

[Dago]

Transistor amplifiers are rarely employed nowadays. For most applications opamps are much better. There are some specialty applications like low-noise amplifiers and such where transistors are used. Also for audio stuff.

[Zero999]

I've left out emitter capacitors for AC gain enhancement on purpose.

Nobody uses this anymore, it's a relict from the times when transistors were expensive. Today, you can design amplifiers that are purely DC, simply because the devices are so cheap

Really? Why would we not be interested in gain enhancement? My understanding is that high frequency AC signals bypass the emitter resistor and thus gain is improved.

Gain is increased, at the expense of massive distortion, especially when the output voltage swing is high. The is because the transconductance is a function of the collector current which, in an ordinary common emitter amplifier, varies as the voltage on the collector resistor changes. With an emitter bypass capacitor, the change in transconductance alters the voltage gain massively, as the output voltage changes. Emitter degradation makes gain constant and the change in transconductance unimportant.

I know op-amps are basically perfect DC amplifiers.

Nowadays very few bother with discrete common emitter amplifiers. Op-amps are the way forward.

[orolo]

CE amplifiers are a basic building block. It's not hard to design working CE amps. They are useful for small signal, AC coupled, medium gain inverting amplifiers at moderate frequencies and medium input-output impedances. There are cures for all these restrictions (small signal -> feedback, AC -> diff amp, gain -> active load, bw -> cascode, impedance -> buffering / bootstrapping) but all require more transistors or components.

A practical case (I invented the parameters first, and built the amp later): you want to amplify a 50mv top amplitude signal with bandwidth from 100Hz to 100kHz and 3K input impedance. You want a -50 voltage gain, and use little power and one 2N3904. Your working voltage is 9V. Your load impedance is a few K.

First, select a bias point. A collector current Ic=1mA is not bad for a 2N3904 (typical beta > 100, even if Ic=3-5mA would be better, it's somewhat wasteful). To get a good swing, the bias voltage could be around 4.5 volts, at the middle of the working voltage. So let us choose a collector current of 1mA and a collector voltage of 4.5volts.

A good collector resistance will then be 4.5K, since 4.5K@1mA = 4.5 volts drop. That load must be the parallel combination of load resistance and collector resistor.

In order to get 50 voltage gain, the emitter resistor should be 4.5K/50 = 90, which is not good from a bias stability viewpoint. We choose 1K as emitter resistor, and later we will add a capacitor coupled load for AC amplification.

With a 1K DC resistor load, the voltage at the emitter will be 1V, since 1K@1mA = 1V. It's true that emitter current is not equal to collector current, but with a beta > 100 it is good enough. Let us assume beta=100 hereafter. Emitter feedback will take care of beta increases with temperautre.

Since the typical active transistor has a voltage drop of about 0.7 volts, the base will be at 1.7V of voltage. So the resistor divider biasing the base must be at 1.7V. It must be stiff enough to not drop much when feeding the base, to it should conduct at least 100uA (Since Ic = 1mA and beta=100, Ib = 10uA, so 100uA is the minimum for a stiff divider).

A divider providing 100uA from 9V must have a combined resistance of 90K. In order to divide at 1.7V, the upper resistor must be 73K and the lower one must be 17K. This is a simple calculation.

The input impedance of the amplifier will be dominated by the voltage divider, since the small signal impedance looking into the base of the transistor will be beta·Re = 100·1K = 100K, while the resistor divider presents an impedance of 73k||17K = 15.5K. The total input impedance will be in the range of 15K, good enough for a 3K input signal.

Since you want a bandwidth of 100Hz, you need an RC constant at the input that has a knee below 100Hz. A 1uF cap will do: f = 6.2832·15K·1u = 10Hz. A few hundred nF would work as well.

So we have an CE amplifier, coupled by 1uF, with a 73K/17K divider at the base, 4.5K at the collector and 1K at the emitter, and 1mA of collector current. Until now, you get -4.5 gain within the desired parameters.

To increase gain, add a 10uF cap at the emitter, with a 30-80 ohm resistor in series. That gives a bandwidth of 100Hz and a gain of -80 to -40. You need to compensate from the 3K/15K divider at the input from the input impedances, which will cause a little voltage loss. Tweaking this resistor if you want a gain of exactly -50 is the only part that requires tweaking. You can use a pot here.

The result is in the attached spice file. The circuit was computed first, and only the 40 ohms at the load were tweaked from an initial estimation of 60. The bode plot of the amp is also included, to check if it amplifies the desired bandwidth (34dB at 180deg, is about -50 gain) . The amplifier does rather well with a 50mV amplitude sinewave at 1kHz, even if it has a second harmonic at -24dB. I tested the spice analysis at temps from 10C to 70C and the gain didn't vary. The power is below 10mW. It only remains choosing standard resistor values near enough the computed values, and testing the circuit in the real world.

JFET amplifiers are, in my experience, more complicated to design, and the tweaking and experimentating part is much more prominent.

[Benta]

Very nice and detailed example from orolo, and it demonstrates the way of working from the output towards the input and the optimizations at the end.

That being said, I still don't know of any colleagues today using emitter caps for gain enhancement. It's usually more expensive than an additional transistor.

[Zero999]

That being said, I still don't know of any colleagues today using emitter caps for gain enhancement. It's usually more expensive than an additional transistor.

Why would it be more expensive than an additional transistor?

Then, unless you go for a fully differential gain stage, in which case you might as well use an op-amp IC, there's the matter of DC coupling (going by your other post, you want to avoid capacitors) the two stages together, which becomes tricky if the gain is high.

[Benta]

Why would it be more expensive than an additional transistor?

Simply 'cause transistors (eg, standard SOT-23) are dirt cheap today

[orolo]

There are lots of very cheap dual transistors in sot packages, so the two stage amplifier is a win both in price and space. There is the problem of coupling the stages, but with some care it can be done without a capacitor. The art of squeezing a single transistor is a thing of the past: since I'm just a hobbyist, I read all the GE and RCA transistor manuals from the 60s I could get, and enjoy the hacks involved, but I'm sure a serious professional wouldn't go that way.

Now, in my limited experience, op amps can be a nuisance sometimes: with battery low voltage operation, single supply and frequencies well into the kHz range, the jellybeans I usually employ are inadequate or require excessive complexity. There is always a silver bullet IC, but either I don't have it around, or it is too expensive. Sometimes a couple transistors get the job done.

[Zero999]

Why would it be more expensive than an additional transistor?

Simply 'cause transistors (eg, standard SOT-23) are dirt cheap today

There's still the issue of coupling the stages together. Try making an amplifier with a gain of 50, consisting of two stages and a 9V power supply, as above. If you DC couple the stages, to get half the supply on the output, the voltage only needs to change by 90mV on the input, for output will saturate. Setting up a DC bias to this level of accuracy is tricky not possible, considering that V_BE isn't that well controlled. You could aim for a higher emitter voltage and bypass with a capacitor but then you didn't want to do that or you could AC couple the two stages but that's still another capacitor.

Attached is an example of two DC coupled common emitter stages with a total gain of about 50. It's quite difficult to trim the bias voltage to get it both transistors in their active region as it is, before the temperature drift of V_BE is taken into account. The plot shows the collector voltage on Q2, when the temperature is swept from 10°C to 40°C.


Now, let's look at the same circuit with the two stages AC coupled. It will have a higher bandwidth and input impedance, than the single transistor version but there are other tricks to achieve this, than simply sticking two CE amplifiers together.

[orolo]

I've pulled off some cascaded stages that were stable from 10-60 deg, with some gain loss at 70, but getting a gain of -50 was a bit tricky since the first stage conditioned the second. What I'd try is just compensating with a diode in the first stage. Diodes are cheap and have a small footprint.

[IconicPCB]

Fortunately transistors unlike valves come in a coupelo of genders.

PNP/NPN pair topologies allow for high gain dc coupled stages.

[Zero999]

I've pulled off some cascaded stages that were stable from 10-60 deg, with some gain loss at 70, but getting a gain of -50 was a bit tricky since the first stage conditioned the second. What I'd try is just compensating with a diode in the first stage. Diodes are cheap and have a small footprint.

The change in gain isn't that much of a problem. Try plotting the shift in DC bias vs temperature. Your circuit is better than the first one I posted but still worse than the AC coupled design. The diode will also have to be well thermally coupled to the transistor.

[TimNJ]

CE amplifiers are a basic building block. It's not hard to design working CE amps. They are useful for small signal, AC coupled, medium gain inverting amplifiers at moderate frequencies and medium input-output impedances. There are cures for all these restrictions (small signal -> feedback, AC -> diff amp, gain -> active load, bw -> cascode, impedance -> buffering / bootstrapping) but all require more transistors or components.

A practical case (I invented the parameters first, and built the amp later): you want to amplify a 50mv top amplitude signal with bandwidth from 100Hz to 100kHz and 3K input impedance. You want a -50 voltage gain, and use little power and one 2N3904. Your working voltage is 9V. Your load impedance is a few K.

First, select a bias point. A collector current Ic=1mA is not bad for a 2N3904 (typical beta > 100, even if Ic=3-5mA would be better, it's somewhat wasteful). To get a good swing, the bias voltage could be around 4.5 volts, at the middle of the working voltage. So let us choose a collector current of 1mA and a collector voltage of 4.5volts.

A good collector resistance will then be 4.5K, since 4.5K@1mA = 4.5 volts drop. That load must be the parallel combination of load resistance and collector resistor.

In order to get 50 voltage gain, the emitter resistor should be 4.5K/50 = 90, which is not good from a bias stability viewpoint. We choose 1K as emitter resistor, and later we will add a capacitor coupled load for AC amplification.

With a 1K DC resistor load, the voltage at the emitter will be 1V, since 1K@1mA = 1V. It's true that emitter current is not equal to collector current, but with a beta > 100 it is good enough. Let us assume beta=100 hereafter. Emitter feedback will take care of beta increases with temperautre.

Since the typical active transistor has a voltage drop of about 0.7 volts, the base will be at 1.7V of voltage. So the resistor divider biasing the base must be at 1.7V. It must be stiff enough to not drop much when feeding the base, to it should conduct at least 100uA (Since Ic = 1mA and beta=100, Ib = 10uA, so 100uA is the minimum for a stiff divider).

A divider providing 100uA from 9V must have a combined resistance of 90K. In order to divide at 1.7V, the upper resistor must be 73K and the lower one must be 17K. This is a simple calculation.

The input impedance of the amplifier will be dominated by the voltage divider, since the small signal impedance looking into the base of the transistor will be beta·Re = 100·1K = 100K, while the resistor divider presents an impedance of 73k||17K = 15.5K. The total input impedance will be in the range of 15K, good enough for a 3K input signal.

Since you want a bandwidth of 100Hz, you need an RC constant at the input that has a knee below 100Hz. A 1uF cap will do: f = 6.2832·15K·1u = 10Hz. A few hundred nF would work as well.

So we have an CE amplifier, coupled by 1uF, with a 73K/17K divider at the base, 4.5K at the collector and 1K at the emitter, and 1mA of collector current. Until now, you get -4.5 gain within the desired parameters.

To increase gain, add a 10uF cap at the emitter, with a 30-80 ohm resistor in series. That gives a bandwidth of 100Hz and a gain of -80 to -40. You need to compensate from the 3K/15K divider at the input from the input impedances, which will cause a little voltage loss. Tweaking this resistor if you want a gain of exactly -50 is the only part that requires tweaking. You can use a pot here.

The result is in the attached spice file. The circuit was computed first, and only the 40 ohms at the load were tweaked from an initial estimation of 60. The bode plot of the amp is also included, to check if it amplifies the desired bandwidth (34dB at 180deg, is about -50 gain) . The amplifier does rather well with a 50mV amplitude sinewave at 1kHz, even if it has a second harmonic at -24dB. I tested the spice analysis at temps from 10C to 70C and the gain didn't vary. The power is below 10mW. It only remains choosing standard resistor values near enough the computed values, and testing the circuit in the real world.

JFET amplifiers are, in my experience, more complicated to design, and the tweaking and experimentating part is much more prominent.

Just wanted to say thank you so much for this awesome response. Sorry I'm so late. Really helped clear up some of the confusion I was having.

[bson]

But now if you attach a given load (through a coupling cap), whenever the input changes (above a certain frequency), the transistor now "sees" a load attached to its drain. As the voltage at the drain changes, current is either driven into or pulled from the load. To me, it seems like there are some simultaneous equations going on(?). For a given quiescent drain current, how can you quantify the voltage swing at a given load? Do people usually calculate that as part of their design? Rules of thumb? Make RL >> RD?

Congratulations, you just understood why people don't use single transistor voltage gain stages anymore.  They require practically infinite input impedance in the next stage, and/or have really high quiescent currents.  Linearity is very poor, meaning massive waveform distortion (more so with a BJT than FET).  This is exactly why opamps are used instead, priced about the same and with a similar footprint (board real estate needs), but orders of magnitude better linearity and driving ability.  The relatively poor G=Rc/Re amplifier is a thing of the past. *

* except in the domain of audiophoolery where magic transistors steeped from unicorn horns continue to be employed due to their angelsong distortion properties **
** unless tubes are used instead; they glow warmly so surely there are more angels inside

[IconicPCB]

Other than PNP and NPN transistor pairs series feedback and shunt feedback topologies are used quite happily to achieve both high gain and high bandwidthamplifiers with defined properties.

There is nothing unicornish about well designed gain stages.

[SingedFingers]

I learned how to bias transistors using Gordon J. Ritchie's book: Transistor Circuit Techniques. Wonderful book. That and The Art of Electronics 2nd edition. The Student Manual that came with it has step by step methods in it which are rather easy to get along with.

Then I did a degree in electrical engineering and learned precisely bugger all from it other than circuit analysis.

However in the real world of 2017, screw it. Back in the 1960s when transistors really took off, they were pretty shit and ICs didn't exist. Now we live in the amazing world of opamps and comparators with incredible slew rates, GBWP of GHz, amazing CMRR and PSRR.

Occasionally I'll sit down and play with the things for the sake of interest, but not much past that.

[TimNJ]

But now if you attach a given load (through a coupling cap), whenever the input changes (above a certain frequency), the transistor now "sees" a load attached to its drain. As the voltage at the drain changes, current is either driven into or pulled from the load. To me, it seems like there are some simultaneous equations going on(?). For a given quiescent drain current, how can you quantify the voltage swing at a given load? Do people usually calculate that as part of their design? Rules of thumb? Make RL >> RD?

Congratulations, you just understood why people don't use single transistor voltage gain stages anymore.  They require practically infinite input impedance in the next stage, and/or have really high quiescent currents.  Linearity is very poor, meaning massive waveform distortion (more so with a BJT than FET).  This is exactly why opamps are used instead, priced about the same and with a similar footprint (board real estate needs), but orders of magnitude better linearity and driving ability.  The relatively poor G=Rc/Re amplifier is a thing of the past. *

* except in the domain of audiophoolery where magic transistors steeped from unicorn horns continue to be employed due to their angelsong distortion properties **
** unless tubes are used instead; they glow warmly so surely there are more angels inside

Haha yeah in simulation and in practice, I found adding a load other than a pretty large one threw off the bias as I had intended. I'm working on high performance front end for an ECG for my senior project and we're using an INA and a few op-amps and the ease of implementation for the performance is just amazing.