Author Topic: MicroSD + ISP on SPI bus w/ level translation  (Read 3484 times)

0 Members and 1 Guest are viewing this topic.

Offline StarlordTopic starter

  • Frequent Contributor
  • **
  • Posts: 325
  • Country: us
MicroSD + ISP on SPI bus w/ level translation
« on: February 16, 2015, 06:25:51 pm »
.
« Last Edit: July 14, 2016, 12:12:01 pm by Starlord »
 

Offline Seppy

  • Supporter
  • ****
  • Posts: 189
  • Country: au
  • Curious
Re: MicroSD + ISP on SPI bus w/ level translation
« Reply #1 on: February 17, 2015, 01:25:49 pm »
When the uC's reset line is active all lines on the uC's are inputs, this means that at this time (Before the programming enable command is transmitted) your all sweet, because MISO is high impedance and pulled up to 3V3 by the 3V3 pullup.
As you have seen after the uC starts using the MISO things might get problematic as the uC in this case is indeed the slave and begins to output 5V (OHH NO).
A zener between two resistors wouldn't be an absolutely terrible course of action but...  :-\

Depending on your rails regulation I wouldn't expect the 3V rail to be varied significantly. At most your getting i=(5-3)/10000=2/10000=200uA, not a lot. If your 3V voltage regulation has a series diode or equivalent on its output your rail will likely raise slightly indeed, the higher the load the less it will raise. Its a voltage div between load and pullup, if the divided value is greater than 3v3-Vf then yeah the 3v3 supply will be dioded away.  >:(

If for some strange reason the SD card MISO was low, and the MISO on the micro was trying to drive high that is where i see a problem.

When Reset is applied to the target AVR microcontroller, the MISO pin is set up to be an input
with no pull up. Only after the “Programming Enable” command has been correctly transmitted
to the target will the target AVR microcontroller set its MISO pin to become an output. During this
first time, the In-System programmer will apply its pull up to keep the MISO line stable until it is
driven by the target microcontroller.

http://www.atmel.com/images/doc0943.pdf
 

Offline StarlordTopic starter

  • Frequent Contributor
  • **
  • Posts: 325
  • Country: us
Re: MicroSD + ISP on SPI bus w/ level translation
« Reply #2 on: February 17, 2015, 09:09:13 pm »
.
« Last Edit: July 14, 2016, 12:12:19 pm by Starlord »
 

Offline Seppy

  • Supporter
  • ****
  • Posts: 189
  • Country: au
  • Curious
Re: MicroSD + ISP on SPI bus w/ level translation
« Reply #3 on: February 18, 2015, 12:59:58 pm »
That circuit is simulating without added series resistors, the two resistors are the port output resistance and the input resistance of the sd card.
While the device has been surviving it is reaching 4.02V (3.3+0.72) at the MISO input. While the SD internal protection may survive this SD cards are typically only rated to 3.6V and while I may have missed it in my readings I don't think that cards guarantee survival at 4.02V, while it may be the case that most do survive some may not.
I would add a couple cents, splash out on a zener and a resistor, an extra channel on your level shifter (need bidirectional type though), if your bit bashing already then you could get a single MOSFET in the attached picture (I didn't draw it very well  :( ) you would have to invert your MISO stuff in the uC firmware though, you would still need the pullup on the SD side.


As for the speed you can have a look at the standards, there are many factors that affect speed, https://www.sdcard.org/downloads/pls/ (I think that is the site to go to for that).

I had a quick look through the above, didn't really find a way to good model the SD card inputs so, not really sure about the speed in terms of a calculation.
« Last Edit: February 18, 2015, 01:01:44 pm by Seppy »
 

Offline StarlordTopic starter

  • Frequent Contributor
  • **
  • Posts: 325
  • Country: us
Re: MicroSD + ISP on SPI bus w/ level translation
« Reply #4 on: February 19, 2015, 07:44:38 pm »
Yeah, I know that simulation was without an added series resistor.

I thought there was an issue with using voltage dividers, like excess current draw or something, but after thinking about it and re-reading the thread on the Arduino forum it seems that's not the case.  The problem with them is when people use values that are too large.   This causes the rise times to be too long at high bus frequencies thanks to the capacitance on the card's inputs which are typically higher than 10pF.

This simulation shows that at an 8MHz bus speed, and with a 10pF input capacitance, a 470/1K voltage divider should do the job, and a divider as low as 200/410 could be used without exceeding the Atmega pin's current rating (pins are rated for over 20mA, but the 200/410 combo draws only 10mA peak and 4mA average:
http://www.partsim.com/simulator#27747

More importantly, it limits the voltage to 3.35V.

So a voltage divider it is, I guess!
 

Offline Seppy

  • Supporter
  • ****
  • Posts: 189
  • Country: au
  • Curious
Re: MicroSD + ISP on SPI bus w/ level translation
« Reply #5 on: February 20, 2015, 07:40:33 am »
While a voltage divider will likely be perfectly functional it does result in substantial wasted power.

P=V^2/R=5^2/(200+410)=41mW worst case

I'm guessing though that isn't an issue. The advantage of the FET arrangement is that it doesn't allow the system to have 2 slave devices with potentially active MISO lines, likely not really a problem anyway though :)
 

Offline StarlordTopic starter

  • Frequent Contributor
  • **
  • Posts: 325
  • Country: us
Re: MicroSD + ISP on SPI bus w/ level translation
« Reply #6 on: February 20, 2015, 10:10:02 am »
Quote
While a voltage divider will likely be perfectly functional it does result in substantial wasted power.

Substantial?  With a 470/1K combination (the one I'll be using), it draws 0.5mA when the pin is low, and 3.3mA when the pin is high.   On average that's 1.9mA which is less than my power LED is drawing.

And even with 200/410, it's still 0.5mA when low, and 7.8mA when high.  So on average, 4mA.  But only during access.  And when the card is being accessed the current draw for that will be like 50-100mA so you're talking like a 5-10% increase in power consumption. 

Now, if I were to do this for all the data lines, and I were to use the 200/410 values then it would add up, but I'm only using this on MISO.  Which btw I believe goes open-collector when the card isn't being accessed, so there wouldn't be a constant 0.5mA current draw from that being low all the time either.

I mean yeah, it's not ideal, and if I were running on a coin cell battery I would want so avoid an additional 2mA of draw during accesses, but I don't really have space on the board to add a fet or diode.  And the board design was basically done when I realized I needed to add this protection.  So the divider will have to do. :)
 


Share me

Digg  Facebook  SlashDot  Delicious  Technorati  Twitter  Google  Yahoo
Smf