Author Topic: Dual slope ADC improvement  (Read 1369 times)

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Offline namster

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Dual slope ADC improvement
« on: September 20, 2019, 03:24:31 pm »
Hi All,
I try to design a 4 or 5 digit ADC, I chose for this a Dual slope Topology which have the advantage of high resolution and low sampling frequency, the schematic in attachments is the first version, but it doesn't give a probate result, I estimated the resolution about 2 digit 1/2 for full scale of 2.5V the resolution was about 100mV, the ADC is controller by a PIC24FJ which is clocked by internal RC with PLL loop that give a frequency of 32Mhz, the timers have a resolution of 16bits, how can I improve the resolution?

« Last Edit: October 02, 2019, 09:06:08 pm by namster »
 

Offline duak

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Re: Dual slope ADC improvment
« Reply #1 on: September 20, 2019, 04:28:14 pm »
Is the Z switch of U20 supposed to reset the Integrator formed by U19B?  I see an unexpected connection of the -15V supply and U19B output.

Where are VCC & GND of U20 connected?

The LM311 comparator U21 has an open collector output.  The pullup resistor R35 can introduce uncertainty when it is too large.  I would try reducing it to 4K7 or even lower - the data sheet shows values of 500R to 1K0.
 

Offline Kleinstein

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Re: Dual slope ADC improvment
« Reply #2 on: September 20, 2019, 04:34:08 pm »
The zener diode D6 is a problem: Zeners tend to already leak well before there nominal voltage. This would cause nonlinear response.

The input resistor R23 is rather small with 1 K. The switch resistor can be on the order of 100 Ohms and temperature depended and also slightly nonlinear. So for the HC4053 switch I would consider some 20 K as the lower useful limit, maybe 5-10 K if there is compensation from the input and reference.
Using a much lower resistor for the input than for the references is more like a problem than really helping. It shortens the integration time, but causes problems: for mains hum suppression the integration time should ideally be 20 ms or a multiple of that. The rundown phase should ideally not be much longer, as the FET OPs in the integrator have quite some 1/f noise. For 20 ms chances are the integration cap would need to be larger.
Normally dual slope uses the same resistor for integration and the reference - so one part less that needs very precise.

The way 1/3 of the 4053 is used to reset the integrator, the voltage range of the integrator is rather limited.
Using the switches in a current steering mode, sending the current to ground or the integrator allows to use the 4053 switches even for higher signal and reference voltages. As there is already a +-15 V supply, I would prefer to have the ADC with something like a +-10 V (or just 10 V) input range. This makes the OP noise less critical.

For just a 4-5 digit target there is no real need for  2 OP integrator, just 1 OP should be good enough. In the current form the divider R31/R32 is way off, which makes the integrator slow to settle at the input. If using the 2 nd OP at all the right divider would be more like 1 K and 10K.

For the µC the internal RC clock may not be that good. Also the PLL may add some jitter - though maybe no that relevant at the target level. Anyway it is relatively easy to use a direct crystal clock for the µC.

A dual slope implementation without major flaws with the given OPs / switches should be capable to get about 4-5 digit resolution, more gets increasingly difficult. The limit should not be due to the timer resolution but is more due to effects like OP offset drift, noise and dielectric absorption in the integration cap.

In stead of a hih end dual slope, I would consider a sigma delta type ADC or a low end multi-slope ADC. It needs more complicated software, but avoid the DA limit.


P.S.  Just saw the 50 K resistor between the switch and the integrator:  so the resistor is not too small and essentially the same resistance is used.
« Last Edit: September 20, 2019, 04:38:13 pm by Kleinstein »
 

Online imo

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Re: Dual slope ADC improvment
« Reply #3 on: September 20, 2019, 05:06:18 pm »

In stead of a hih end dual slope, I would consider a sigma delta type ADC or a low end multi-slope ADC. It needs more complicated software, but avoid the DA limit.


FYI - 6 pins ADS1110 does +/- 32768 counts (16bit), differential inputs +/- 2.048V, 1-8x PGA, 15-260 measurements/sec, I2C, internal 5ppm/C reference.

840086-0
« Last Edit: September 20, 2019, 05:11:58 pm by imo »
 

Offline namster

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Re: Dual slope ADC improvment
« Reply #4 on: September 22, 2019, 03:14:08 pm »
thanks All ,
@duak yes the Z siwtch is used to reset the integrator by shorting the capacitor , and yes  the -15V is unexpected connection its surley a mistake , the VCC is conected to 5V out of U17 , the input will theorecly never exceed the 2.6V so normally it will not be a problem .
i used diffrents values of resistor and the value that i chose is 220 Ohm isn't too small
@Kleinstein
the zener Diode is used to limit the voltage at 2.6V , in my instrument in the case where no resistance to be measured is connected the voltage rise to 15V wich can damage the circuit i didn't find any other solution to correcte that , i am waiting for the Printed circuit board to do some test , for now i simulate the circuit with taking in consdieration all that everything you said .
@imo
 I would have liked to use directly a Delta sigma ADC but isn't available in my country !
 

Offline Kleinstein

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Re: Dual slope ADC improvment
« Reply #5 on: September 22, 2019, 03:52:20 pm »
Even if a ready made SD ADC is no available, one could still use the µC to control a simple slow SD ADC. The software is a little more complicated, but the HW side can be even a little simpler than the dual slope version shown. Modern µC usually contain an comparator an reasonable speed 8-12 bit ADC that can be used.

The HC4053 are usually relatively robust and the 4053 internal diodes a the inputs can to a large part replace the zener diode. It may need a zener at the supply than and a little larger resistor to limit the current. The normal function of the 4053 switches would not wort in case of overload, but this would not be a real problem.
 

Online imo

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Re: Dual slope ADC improvment
« Reply #6 on: September 22, 2019, 05:53:06 pm »
Here is a simulation of a Multislope ADC, which could be doable (ie 4-5 digits +/- 2.5Vref) with your components and the pic24..

https://www.eevblog.com/forum/projects/multislope-design/msg2561853/#msg2561853

 

Offline namster

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Re: Dual slope ADC improvment
« Reply #7 on: September 23, 2019, 02:59:09 pm »
@Kleinstein
i need for my application at least 13 bit resolution and that can't be done with internal ADC of µC that why i try to realize a Dual slope AD,in the weekend i will test the 2nd Version of schematic
 @imo
Oh ! that very interessting topics with many informations , i will take  note
 

Offline Kleinstein

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Re: Dual slope ADC improvment
« Reply #8 on: September 23, 2019, 05:47:12 pm »
The µC internal ADC is limited resolution, but it can be used as a building block for a higher resolution integrating ADC of some type.

One is a simple SD type ADC: The µC internal ADC is used to read the integrator output and controls a PWM from the µC to feed back the reference to the integrator.  It is a little more math behind it than the simple dual slope, but it can be low HW effort and high resolution (e.g. 16 Bit).

For just 16 Bit the multi-slope version like in the link IMO showed can be even simpler:  a 1 OP integrator is sufficient and no real need for the extra amplifier behind the integrator. This is especially true if operated like the ADC in the HP34401 DMM:  continuous integrating and using the µC internal ADC for extra resolution.  This is actually not that much different from the SD version described above.

The classical way with run-up and run-down phase should also work. For only 16 Bit resolution there is not even need for a 2nd slower slope in rundown. As a compromise for simple HW one can skip the reset phase and use the final state after rundown as an approximate starting point.

The schematic from the start has some flaws and weak points, but the dual slope principle should still be good enough for 13 bits. The same hardware (may need a smaller integration cap) can be used in a dual slope mode and with a multi_slope run-up version as a possible later upgrade.
 

Online imo

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Re: Dual slope ADC improvment
« Reply #9 on: September 23, 2019, 07:01:43 pm »
Here is the Basic Runup V20 simulation.
It consists of 4053, integrator opamp, and the comparator (and +/- 2.5Vref sources).
The rest is in the PIC.
You may add the amplif opamp for PIC ADC (Kleinstein's version).
The opamps do not need +/-15V in your case.

The runup sim counts (1000 total counts in 20ms "integration" timeframe):

2V input   901 counts
0V input   501 counts
-2V input  101 counts

LTspice source included below.
All you need is to add the run-down phase..
And to write the PIC code..  :D
« Last Edit: September 23, 2019, 07:34:14 pm by imo »
 

Offline Kleinstein

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Re: Dual slope ADC improvment
« Reply #10 on: September 23, 2019, 07:27:11 pm »
For a simple solution the comparator and logic part can be inside the µC.
Ideally, for better SNR, the reference voltages should be higher than +-2.5 V, more like +-5 V to +-15 V.

The OP used for the integrator does not need to be very special. However with a cheap OP (e.g. like TL072) or for highest precision it may need an extra buffer and MUX before the actual ADC to alternate between the actual input and a zero measurement. Ideally one would also allow to directly read the reference.
 

Online imo

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Re: Dual slope ADC improvment
« Reply #11 on: September 23, 2019, 07:48:58 pm »
Still you have to reset the integration cap when not capturing the residual voltage levels at the beginning and at the end of the 20ms frame, imho..
An 2n7000 shorting the integrator input against gnd, perhaps?
« Last Edit: September 23, 2019, 07:51:21 pm by imo »
 

Offline Kleinstein

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Re: Dual slope ADC improvment
« Reply #12 on: September 24, 2019, 06:09:55 am »
The integrator reset is not absolutely needed. At lower resolution one can still assume that the rundown with comparator gives a reasonable zero. If drift is an issue one might use some extra delay and a 2 nd rundown to get less critical timing.

Just a switch to ground at the integrator input would not give a reset. The reset would need a feed-back from the integrator output to the input. So just a MOSFET will not work well. There is more like a chance to use the path through the MUX before the actual ADC and use one input for the reset.
A simple dual slope version could use just a MUX - Buffer - integrator configuration. So no 4053 but more like 4051 for switching. For extra resolution one could use a 2 nd slow slope.  This should also be sufficient to get some 16 bit resolution, though with limited INL due to the capacitor DA.
 

Offline namster

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Re: Dual slope ADC improvment
« Reply #13 on: September 25, 2019, 08:30:11 pm »
I'm back , i recived my PCB today and i start with soldering the component , in first i will test the Dual slope ADC with making some measurment and try to get the best of it performance .
@imo
that's very interessting design , i plane to make a PCB with single in line connection for both of dual and multislope with integring a PIC16f in SMD package
@Kleinstein
in case of using a refrence like the LM399 with a 2% initial tolerance its necessary to calibrate it ? , the other point that concerns me is the clock stability of microcontroller , is the XO sufficient or TCXO ?
 

Offline Kleinstein

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Re: Dual slope ADC improvment
« Reply #14 on: September 26, 2019, 06:00:42 am »
For essentially any high resolution ADC one would need a calibration, as the absolute accuracy of the references is not that good.
For some ADCs (most dual slope, SD-Chips) the ADC gain is relative well known, but others (including most multi-slope solutions) the ADC gain is not so well known and depends on resistor ratios.

For the clock a normal crystal clock is sufficient. At the high end (e.g. 8 digits) one may have to look at the clock jitter and a poor quality XO may contribute a little noise. Still not real need for an TCXO, a good classical XO is sufficient. I got away with just the crystal connected to an AVR µC, with very little noise due to clock jitter.  More problematic can be a PLL that is used in some µCs or FPGAs for the clock.

One may use a circuit made for a multi-slope ADC in a dual slope way. However the MS-ADC usually uses different resistors for the references and input. The dual slope DAC can use the same resistor and is this more stable in ADC gain. So using the MS-hardware in dual slope more is not very useful - except for debugging and initial tests.  Usually the dual slope ADC is thus a little simpler and needs less precision resistors. However the dual slope version is usually higher noise and limited in linearity by DA.
 

Online imo

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Re: Dual slope ADC improvment
« Reply #15 on: September 26, 2019, 06:55:57 am »
@imo
that's very interessting design , i plane to make a PCB with single in line connection for both of dual and multislope with integring a PIC16f in SMD package
That is a simulation only, where the digital part (generating the switching signals) is hidden in the LTspice's pulse definitions.
That has to be converted into a PIC code (not easy, btw).
Anyhow, a real implementation would require some elaboration of the schematics, sure.
 

Offline mrjoda

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Re: Dual slope ADC improvment
« Reply #16 on: September 26, 2019, 12:20:33 pm »
What about small CPLD or FPGA used as precise counter + generating clock? and then communication with MCU over some UART or SPI or so.
 

Online jaromir

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Re: Dual slope ADC improvment
« Reply #17 on: September 26, 2019, 12:43:45 pm »
Yes, that is always possible. In this long topic https://www.eevblog.com/forum/projects/multislope-design/ few possiblities is mentioned. Apart from that, in topic https://www.eevblog.com/forum/metrology/diy-6-5-digit-voltmeter/ is complete 6,5 digit voltmeter built on multislope ADC, with sources and PCB files. Inguard logic is driven by single CPLD, sending ADC results to main MCU via isolated interface. I believe CPLD of small FPGA is the way to go here,

On the other hand, OP has difficulties to source some components, that may also limit availability of programmable logic for him. When I started with integrating ADCs, I did a lot of experiments with simple dual slope circuits, driven by interrupt based state machine on low-end PIC16 MCU and achieved 15-16 bits of usable resolution. Nothing too complicated, probably one page worth of C source code.
My hobby projects: https://hackaday.io/jaromir ----------- http://jaromir.xf.cz/
 

Offline namster

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Re: Dual slope ADC improvment
« Reply #18 on: October 02, 2019, 07:35:46 pm »
after a while , i finally test my dual slope , I had to add a voltage follower opamp to stabilize the vin Voltage i used a potentiometer to set voltage tomorrow i will do some precision measurement in laboratory  the university  .
 the ADC reached 100µV resolution , i have tested multiple value of the capacitor and time of integration ( 100nF 470nF and 1uF no polarised ) i finally chose a 100mS integration time with 100K Resistor and 100nF capacitor ( Philips Metallized Polyester Film Capacitors ) is that a good choise ?

i tried to estimate the resolution by this way , is that correct ?
Quote
Full scale = 10V
quantum =100µV
Number of Point  = (10/100µV)-1)=99999
Resolution=ln(99999)/ln(2)=16.68 bits
can I still improve it? with a stable clock and CPLD or FPGA? or that is the limit of a dual slope ADC and I have to continue with Multislope?
 

Offline Kleinstein

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Re: Dual slope ADC improvement
« Reply #19 on: October 03, 2019, 08:23:34 am »
16 bit resolution is already quite good for a dual slope ADC. One may get a little higher resolution, but getting corresponding good INL gets really hard. For lower noise it may need high grade parts, like better OPs in the integrator. For the clock a simple crystal based clock is good enough, just an RC clock, like the µC internal clock may contribute a little to the noise. It should be possible to get accurate timing with sufficient resolution from the µC, but the programming can be tricky (e.g. ASM).

One main limitation of the dual slope converter in nonlinearity due to dielectric absorption. So the cap should be a low DA type like polypropylene. Even than DA can limit the accuracy. So a polyester cap is a poor choice.

The multi-slope ADC is a way to reduce the DA problem quite a bit. A smaller integration cap also reduces the effect of higher frequency noise.
However the usual multi-slope design has one downside: it uses separate resistors for the input and the references. So the ADC gain depends on the resistor ratio and is thus less stable.

100 ms integration time is a reasonably compromise between the 1/f noise and resolution.  With sufficient timing resolution one may get less noise with shorter conversions and averaging.

There is a not so well know way in between dual-slope and multi-slope: one can use multiple shorter dual slope like cycles, but without the integrator reset and only after some 10 such cycles do a reset. This reduces the DA effect by about the number of cycles, possibly more with modified control to reduce the average capacitor voltage even more. It can use the same analog hardware, just different control.

Another critical part in the dual slope ADC is the reset and auto-zero phase. How is that implemented ?
 

Offline namster

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Re: Dual slope ADC improvement
« Reply #20 on: October 03, 2019, 09:20:24 pm »
for now I am very satisfied by result of my design, it's largely enough for my micro ohmmeter application, the only good capacitor that I found in my stock is a 100nF MKT (Polyester film capacitors (PET)) that have theoretically 0.2 to 0.5% DA, in second step I will try to find a PP capacitor, I also reduced the integration time to 40 ms it thinks that is also reasonable chose that is a multiple of 20mS.
for resetting the capacitor I used the third switch of 4053 which is used to short the capacitor is that the right way of resetting capacitor?  also do auto-zero phase with shorting the capacitor after 100 measurement cycle .
 

Offline moffy

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Re: Dual slope ADC improvement
« Reply #21 on: October 04, 2019, 04:50:07 am »
Polystyrene and NPO caps also have low dielectric absorbtion. The gold standard is teflon but they are almost impossible to get.
 

Offline Kleinstein

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Re: Dual slope ADC improvement
« Reply #22 on: October 04, 2019, 09:24:29 am »
From the dielectric absorption polypropylene, polystyrene and NP0 are about equal. For the relative large cap needed with a dual slope ADC, the usual choice is polypropylene. Modern NP0 MLCC may be a new option, but I have not seen dielectric absorption data for them.
Polyester caps have about 10 times the dielectric absorption.

Resetting the capacitor with a switch in parallel (one may want some resistance to protect the switch) is one option. It does not include a possible offset of the comparator. This is not a problem when using "digital" offset compensation by doing a zero reading from while to while. Alternatively in the case of the milli-ohms meter one could use a pseudo differential reading.

Using the 4053 to shorten the capacitor limits the useful voltage range for he integrator, as the voltage must not exceed the supply at the 4053.
Depending on the supply this may be acceptable. As the 4053 may have quite some leakage one may want to use a slightly lower resistance for the integrator (so more like 30 K instead of 100 K).

To reduce the effect of DA one could use a modified procedure / software and use the multiple dual slope cycles. Especially a case with 2 cycles:
start with zero and a first integration (e.g. 20 ms) followed by the disintegrate phase. So this is essentially a dual slope cycel.  Than as a special extend the reference phase by some 90% minus some reserve so that the integrator swings to the opposite sign. Than a 2 nd 20 ms integration periode and final rundown complete the conversion. This could reduce the DA effect - for the slow part by about a factor of 10.
 

Online imo

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Re: Dual slope ADC improvement
« Reply #23 on: October 04, 2019, 09:32:12 am »
Btw, the standard deviation of your above output is 205uV.
 

Offline namster

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Re: Dual slope ADC improvement
« Reply #24 on: October 04, 2019, 06:42:45 pm »
the lowest value of DA the lowest value is that of PP capacitor a comparaison can be found in this link http://www.avx.com/docs/techinfo/General/dielectr.pdf
https://www.wima.de/en/our-product-range/smd-capacitors/smd-pet/comparison-of-dielectrics/
for MLCC NP0 the DA is estimated about 0.5 %
https://web.archive.org/web/20120201110951/http://www.holystonecaps.com/PDF/TechNotes/200712181125470.Capdielectriccomp3.pdf#

the Absolute maximal voltage of 74HC4053 is 10V with condition of VCC-VEE= 10V is i use a 2.5V vref the maximal positive input voltage is 7.5V , for that i have to chose a adequate value of Capacitor , C=(integrationTime*Vref)/(Vsat*R) , so i chose a Integration time of 40ms  Vsat of 5V Vref=2.5V , C= 660nF with R=30kOhm , I therefore conclude that the first cause of limitation of the useful voltage range for the integrator is the max voltage supply of 74HC4053 .
i juste have question can i measure negative voltage with dual slope ? , i think no !
also i would like to estimate the INL of this ADC , i think i will use a  Data Acquisition (DAQ) and a Reference voltage with multi turn Potontimeter to set a precision Voltage , i will collect some point and finally calculating a   regression Polynomial or linear !
@imo
200µV is acceptable value for a full scale of 10V and resolution of 1mV i estimated a 16 bits resolution ( 10000 point )
 


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