Electronics > Projects, Designs, and Technical Stuff
Dual slope ADC improvement
Kleinstein:
For a simple solution the comparator and logic part can be inside the µC.
Ideally, for better SNR, the reference voltages should be higher than +-2.5 V, more like +-5 V to +-15 V.
The OP used for the integrator does not need to be very special. However with a cheap OP (e.g. like TL072) or for highest precision it may need an extra buffer and MUX before the actual ADC to alternate between the actual input and a zero measurement. Ideally one would also allow to directly read the reference.
iMo:
Still you have to reset the integration cap when not capturing the residual voltage levels at the beginning and at the end of the 20ms frame, imho..
An 2n7000 shorting the integrator input against gnd, perhaps?
Kleinstein:
The integrator reset is not absolutely needed. At lower resolution one can still assume that the rundown with comparator gives a reasonable zero. If drift is an issue one might use some extra delay and a 2 nd rundown to get less critical timing.
Just a switch to ground at the integrator input would not give a reset. The reset would need a feed-back from the integrator output to the input. So just a MOSFET will not work well. There is more like a chance to use the path through the MUX before the actual ADC and use one input for the reset.
A simple dual slope version could use just a MUX - Buffer - integrator configuration. So no 4053 but more like 4051 for switching. For extra resolution one could use a 2 nd slow slope. This should also be sufficient to get some 16 bit resolution, though with limited INL due to the capacitor DA.
namster:
I'm back , i recived my PCB today and i start with soldering the component , in first i will test the Dual slope ADC with making some measurment and try to get the best of it performance .
@imo
that's very interessting design , i plane to make a PCB with single in line connection for both of dual and multislope with integring a PIC16f in SMD package
@Kleinstein
in case of using a refrence like the LM399 with a 2% initial tolerance its necessary to calibrate it ? , the other point that concerns me is the clock stability of microcontroller , is the XO sufficient or TCXO ?
Kleinstein:
For essentially any high resolution ADC one would need a calibration, as the absolute accuracy of the references is not that good.
For some ADCs (most dual slope, SD-Chips) the ADC gain is relative well known, but others (including most multi-slope solutions) the ADC gain is not so well known and depends on resistor ratios.
For the clock a normal crystal clock is sufficient. At the high end (e.g. 8 digits) one may have to look at the clock jitter and a poor quality XO may contribute a little noise. Still not real need for an TCXO, a good classical XO is sufficient. I got away with just the crystal connected to an AVR µC, with very little noise due to clock jitter. More problematic can be a PLL that is used in some µCs or FPGAs for the clock.
One may use a circuit made for a multi-slope ADC in a dual slope way. However the MS-ADC usually uses different resistors for the references and input. The dual slope DAC can use the same resistor and is this more stable in ADC gain. So using the MS-hardware in dual slope more is not very useful - except for debugging and initial tests. Usually the dual slope ADC is thus a little simpler and needs less precision resistors. However the dual slope version is usually higher noise and limited in linearity by DA.
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