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Dual slope ADC improvement

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iMo:

--- Quote from: namster on September 25, 2019, 08:30:11 pm ---@imo
that's very interessting design , i plane to make a PCB with single in line connection for both of dual and multislope with integring a PIC16f in SMD package

--- End quote ---
That is a simulation only, where the digital part (generating the switching signals) is hidden in the LTspice's pulse definitions.
That has to be converted into a PIC code (not easy, btw).
Anyhow, a real implementation would require some elaboration of the schematics, sure.

mrjoda:
What about small CPLD or FPGA used as precise counter + generating clock? and then communication with MCU over some UART or SPI or so.

jaromir:
Yes, that is always possible. In this long topic https://www.eevblog.com/forum/projects/multislope-design/ few possiblities is mentioned. Apart from that, in topic https://www.eevblog.com/forum/metrology/diy-6-5-digit-voltmeter/ is complete 6,5 digit voltmeter built on multislope ADC, with sources and PCB files. Inguard logic is driven by single CPLD, sending ADC results to main MCU via isolated interface. I believe CPLD of small FPGA is the way to go here,

On the other hand, OP has difficulties to source some components, that may also limit availability of programmable logic for him. When I started with integrating ADCs, I did a lot of experiments with simple dual slope circuits, driven by interrupt based state machine on low-end PIC16 MCU and achieved 15-16 bits of usable resolution. Nothing too complicated, probably one page worth of C source code.

namster:
after a while , i finally test my dual slope , I had to add a voltage follower opamp to stabilize the vin Voltage i used a potentiometer to set voltage tomorrow i will do some precision measurement in laboratory  the university  .
 the ADC reached 100µV resolution , i have tested multiple value of the capacitor and time of integration ( 100nF 470nF and 1uF no polarised ) i finally chose a 100mS integration time with 100K Resistor and 100nF capacitor ( Philips Metallized Polyester Film Capacitors ) is that a good choise ?

i tried to estimate the resolution by this way , is that correct ?

--- Quote ---Full scale = 10V
quantum =100µV
Number of Point  = (10/100µV)-1)=99999
Resolution=ln(99999)/ln(2)=16.68 bits

--- End quote ---
can I still improve it? with a stable clock and CPLD or FPGA? or that is the limit of a dual slope ADC and I have to continue with Multislope?

Kleinstein:
16 bit resolution is already quite good for a dual slope ADC. One may get a little higher resolution, but getting corresponding good INL gets really hard. For lower noise it may need high grade parts, like better OPs in the integrator. For the clock a simple crystal based clock is good enough, just an RC clock, like the µC internal clock may contribute a little to the noise. It should be possible to get accurate timing with sufficient resolution from the µC, but the programming can be tricky (e.g. ASM).

One main limitation of the dual slope converter in nonlinearity due to dielectric absorption. So the cap should be a low DA type like polypropylene. Even than DA can limit the accuracy. So a polyester cap is a poor choice.

The multi-slope ADC is a way to reduce the DA problem quite a bit. A smaller integration cap also reduces the effect of higher frequency noise.
However the usual multi-slope design has one downside: it uses separate resistors for the input and the references. So the ADC gain depends on the resistor ratio and is thus less stable.

100 ms integration time is a reasonably compromise between the 1/f noise and resolution.  With sufficient timing resolution one may get less noise with shorter conversions and averaging.

There is a not so well know way in between dual-slope and multi-slope: one can use multiple shorter dual slope like cycles, but without the integrator reset and only after some 10 such cycles do a reset. This reduces the DA effect by about the number of cycles, possibly more with modified control to reduce the average capacitor voltage even more. It can use the same analog hardware, just different control.

Another critical part in the dual slope ADC is the reset and auto-zero phase. How is that implemented ?

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