Electronics > Projects, Designs, and Technical Stuff
Dual slope ADC improvement
namster:
for now I am very satisfied by result of my design, it's largely enough for my micro ohmmeter application, the only good capacitor that I found in my stock is a 100nF MKT (Polyester film capacitors (PET)) that have theoretically 0.2 to 0.5% DA, in second step I will try to find a PP capacitor, I also reduced the integration time to 40 ms it thinks that is also reasonable chose that is a multiple of 20mS.
for resetting the capacitor I used the third switch of 4053 which is used to short the capacitor is that the right way of resetting capacitor? also do auto-zero phase with shorting the capacitor after 100 measurement cycle .
moffy:
Polystyrene and NPO caps also have low dielectric absorbtion. The gold standard is teflon but they are almost impossible to get.
Kleinstein:
From the dielectric absorption polypropylene, polystyrene and NP0 are about equal. For the relative large cap needed with a dual slope ADC, the usual choice is polypropylene. Modern NP0 MLCC may be a new option, but I have not seen dielectric absorption data for them.
Polyester caps have about 10 times the dielectric absorption.
Resetting the capacitor with a switch in parallel (one may want some resistance to protect the switch) is one option. It does not include a possible offset of the comparator. This is not a problem when using "digital" offset compensation by doing a zero reading from while to while. Alternatively in the case of the milli-ohms meter one could use a pseudo differential reading.
Using the 4053 to shorten the capacitor limits the useful voltage range for he integrator, as the voltage must not exceed the supply at the 4053.
Depending on the supply this may be acceptable. As the 4053 may have quite some leakage one may want to use a slightly lower resistance for the integrator (so more like 30 K instead of 100 K).
To reduce the effect of DA one could use a modified procedure / software and use the multiple dual slope cycles. Especially a case with 2 cycles:
start with zero and a first integration (e.g. 20 ms) followed by the disintegrate phase. So this is essentially a dual slope cycel. Than as a special extend the reference phase by some 90% minus some reserve so that the integrator swings to the opposite sign. Than a 2 nd 20 ms integration periode and final rundown complete the conversion. This could reduce the DA effect - for the slow part by about a factor of 10.
iMo:
Btw, the standard deviation of your above output is 205uV.
namster:
the lowest value of DA the lowest value is that of PP capacitor a comparaison can be found in this link http://www.avx.com/docs/techinfo/General/dielectr.pdf
https://www.wima.de/en/our-product-range/smd-capacitors/smd-pet/comparison-of-dielectrics/
for MLCC NP0 the DA is estimated about 0.5 %
https://web.archive.org/web/20120201110951/http://www.holystonecaps.com/PDF/TechNotes/200712181125470.Capdielectriccomp3.pdf#
the Absolute maximal voltage of 74HC4053 is 10V with condition of VCC-VEE= 10V is i use a 2.5V vref the maximal positive input voltage is 7.5V , for that i have to chose a adequate value of Capacitor , C=(integrationTime*Vref)/(Vsat*R) , so i chose a Integration time of 40ms Vsat of 5V Vref=2.5V , C= 660nF with R=30kOhm , I therefore conclude that the first cause of limitation of the useful voltage range for the integrator is the max voltage supply of 74HC4053 .
i juste have question can i measure negative voltage with dual slope ? , i think no !
also i would like to estimate the INL of this ADC , i think i will use a Data Acquisition (DAQ) and a Reference voltage with multi turn Potontimeter to set a precision Voltage , i will collect some point and finally calculating a regression Polynomial or linear !
@imo
200µV is acceptable value for a full scale of 10V and resolution of 1mV i estimated a 16 bits resolution ( 10000 point )
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