Electronics > Projects, Designs, and Technical Stuff
Dual slope ADC improvement
Kleinstein:
One can measure negative voltage with a dual slope ADC, if one has positive and negative references available. Alternatively one can use an offset to the input (e.g. zero at the integrator).
With a +7.5 V and -2.5 V supply would allow only 7.5 V as maximum at the input. The integration cap requirement is set by the maximum input, not the reference voltage. So it would be C=(integrationTime*Vin_max)/(Vsat*R). Vsat depends on where the integrator starts. Starting at 0 and thus allowing 7.5 V at the input there are only 2.5 left for Vsat, if there is no special provision for the reset circuit. So the integration cap would need to be even larger or the resistor larger. 20 ms integration time would also be an option.
For a larger Vsat, one could use a divider or diodes to limit the switch voltage.
To test linearity, at this level the method of choice would normally be a more linear DMM or calibrator / Kelvin-Varlay divider.
The main part to worry about is the large range INL, not so much the DNL.
I would expect that the auto zero (reading a zero input) should be done quite often, possible alternating between the signal and zero unless an AZ OP is used. JFET OPs tend to have quite some 1/f noise and thus a short time since AZ really helps. Thus is may be worth considering 20 ms integration - longer integration may not lead to lower noise. Even than the cycle is allready quite long: 20 ms integrate, 60 ms for disintegrate and a few ms for the capacitor discharge.
duak:
Would it be advantageous to use a zero drift opamp ie., chopper stabilized, for the integrator? This should reduce the 1/f noise but would likely cost something somewhere else. Any thoughts?
BTW, the closest I got to designing a dual slope A/D was to build a 3 1/2 digit DMM using the Siliconix LD110/111 chipset in 1975. Siliconix did the hard work and I just followed their lead. If memory serves it was an integrating design, with a commutating auto-zero and implemented in PMOS + bipolar. The app note was quite good and goes into more detail than the data sheet. There's a link on this site talking about the chipset: https://www.eevblog.com/forum/testgear/quality-multimeters-using-sigma-delta/20/?wap2
Kleinstein:
An AZ OP at the integrator - than likely as a 2 OP integrator, as most of the AZ OPs are relatively slow - could help a little, as it would reduce the 1/f noise. However there would still be the noise of the input buffer, though this could easily be a BJT based OP, as it does not need to be very low bias. The downside of AZ OPs is often noise at higher frequencies - so an alternative AZ mode (in sync with the ADC operation) could be higher performance. However it depends on the length of the cycle - this tends to be relatively long for a dual slope ADC (some 60 ms minimum if the range is 2xV_ref).
A cheap AZ OP (e.g. MCP6V26) has a comparable price tag to a precision JFET OP. However the availability may be a problem in some countries. Otherwise a ready made ADC chip like ICL7135 or MCP3421 or LTC2451 would be easier and cheaper than building a µC controlled dual slope ADC.
A good circuit to look at, building a dual slope ADC, could be the Datron 1061 DMM, that used a dual slope like ADC (though with an additional slow slope). This is about as good as an dual slope ADC could get. It uses a possible alternative way for auto zero, combined with the integrator reset.
The old LD110/111 and LD120/121 are already more multi-slope like than a classical dual slope ADC.
iMo:
fyi - https://www.circuitsonline.net/forum/view/95584
namster:
@Kleinstein
i was wrong , so I corrected the value of Capacitor and resistor by chosing a 680nF and 47k for integration time of 20ms
--- Quote ---Vsat depends on where the integrator starts. Starting at 0 and thus allowing 7.5 V at the input there are only 2.5 left for Vsat,
--- End quote ---
µ
the integration slope is given by Vin/RC so for integration time of Tin the output of integrator will Rise from 0 to a given voltage , for a maximal voltage of 7.5V the output will be 7.5V after Tint i don't understend why you said that there only 2.5 left for Vsat .
Auto zero can be done by reading a grounded input , its less complicated than using a AZ opamp no ?
so now i have to do a calibration of the ADC and finalising this one with add a zero Volt input !
@imo
most of links dont work ! but it give some information thank you !
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